Searched +full:zynq +full:- +full:devcfg +full:- +full:1 (Results 1 – 7 of 7) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx Zynq FPGA Manager10 - Michal Simek <michal.simek@amd.com>14 const: xlnx,zynq-devcfg-1.017 maxItems: 120 maxItems: 123 maxItems: 1[all …]
6 - Introduction7 - Terminology8 - Sequence9 - FPGA Region10 - Supported Use Models11 - Device Tree Examples12 - Constraints82 ---------------- ----------------------------------85 | ----| | ----------- -------- |87 | | W | | | ----------- -------- |[all …]
8 .\" 1. Redistributions of source code must retain the above copyright29 .Nm devcfg30 .Nd Zynq PL device config interface32 .Cd device devcfg35 .Pa /dev/devcfg36 can be used to configure the PL (FPGA) section of the Xilinx Zynq-7000.41 asserts the top-level PL reset signals, disables the PS-PL level shifters,44 When the PL asserts the DONE signal, the devcfg driver will enable the level45 shifters and release the top-level PL reset signals.49 .Bd -literal -offset indent[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (C) 2011 - 2014 Xilinx7 #address-cells = <1>;8 #size-cells = <1>;9 compatible = "xlnx,zynq-7000";12 #address-cells = <1>;13 #size-cells = <0>;16 compatible = "arm,cortex-a9";20 clock-latency = <1000>;21 cpu0-supply = <®ulator_vccpint>;[all …]
1 /*-2 * SPDX-License-Identifier: BSD-2-Clause10 * 1. Redistributions of source code must retain the above copyright30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section31 * of Zynq[all...]
1 /*-2 * SPDX-License-Identifier: BSD-2-Clause10 * 1. Redistributions of source code must retain the above copyright30 * Zynq-700 SLCR driver. Provides hooks for cpu_reset and PL control stuff.33 * Reference: Zynq-700[all...]
1 /*-8 * 1. Redistributions of source code must retain the above copyright29 compatible = "xlnx,zynq-7000";30 #address-cells = <1>;31 #size-cells = <1>;32 interrupt-parent = <&GIC>;38 // Zynq PS System registers.42 compatible = "simple-bus";43 #address-cells = <1>;44 #size-cells = <1>;[all …]