Lines Matching +full:zynq +full:- +full:devcfg +full:- +full:1

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
10  * 1. Redistributions of source code must retain the above copyright
30  * Zynq-700 SLCR driver.  Provides hooks for cpu_reset and PL control stuff.
33  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
66 #define ZSLCR_LOCK(sc)		mtx_lock(&(sc)->sc_mtx)
67 #define	ZSLCR_UNLOCK(sc)		mtx_unlock(&(sc)->sc_mtx)
69 	mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev),	\
71 #define ZSLCR_LOCK_DESTROY(_sc)	mtx_destroy(&_sc->sc_mtx);
73 #define RD4(sc, off) 		(bus_read_4((sc)->mem_res, (off)))
74 #define WR4(sc, off, val) 	(bus_write_4((sc)->mem_res, (off), (val)))
78 SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
79     "Xilinx Zynq-7000");
83 	      "Zynq boot mode");
87 	   "Zynq PSS IDCODE");
91 	   0, "Zynq REBOOT_STATUS register");
95 	   0, "Zynq PS_CLK Frequency");
99 	   0, "Zynq IO PLL Frequency");
103 	   &arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
107 	   &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
133 	/* This has something to do with a work-around so the fsbl will load
134 	 * the bitstream after soft-reboot.  It's very important.
174 /* After PL configuration, enable level shifters and deassert top-level
177  * is controlled by a sysctl in the devcfg driver.
216 		return (-1);
221 	for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
231 		return (-1);
263 		return (-1);
292 		return (-1);
320 		return (-1);
337 			return (-1);
343 	for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) {
353 		return (-1);
387 		return (-1);
404 			return (-1);
419 		div0 = 1;
422 		div1 = 1;
438 		return (-1);
462 		return (-1);
470 	WR4(sc, ZY7_SLCR_FPGA_THR_CNT(unit), 1);
487 		return (-1);
493 	return !(reg & 1);
504 		return (-1);
553 	device_set_desc(dev, "Zynq-7000 slcr block");
570 		"JTAG", "Quad-SPI", "NOR", "(3?)",
578 	sc->dev = dev;
584 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
586 	if (sc->mem_res == NULL) {
604 		 "family: 0x%x sub-family: 0x%x rev: 0x%x",
621 	if (OF_getencprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
683 	if (sc->mem_res != NULL)
685 			     rman_get_rid(sc->mem_res), sc->mem_res);
711 MODULE_VERSION(zy7_slcr, 1);