Lines Matching +full:zynq +full:- +full:devcfg +full:- +full:1
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
10 * 1. Redistributions of source code must retain the above copyright
30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section
31 * of Zynq.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
88 #define DEVCFG_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
89 #define DEVCFG_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
91 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
93 #define DEVCFG_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx);
94 #define DEVCFG_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED);
96 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
97 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
100 "Xilinx Zynq-7000 PL (FPGA) section");
108 static int zy7_en_level_shifters = 1;
111 "Enable PS-PL level shifters after device config");
115 "Zynq-7000 PS version");
133 .d_name = "devcfg",
136 /* Devcfg block registers. */
138 #define ZY7_DEVCFG_CTRL_FORCE_RST (1<<31)
139 #define ZY7_DEVCFG_CTRL_PCFG_PROG_B (1<<30)
140 #define ZY7_DEVCFG_CTRL_PCFG_POR_CNT_4K (1<<29)
141 #define ZY7_DEVCFG_CTRL_PCAP_PR (1<<27)
142 #define ZY7_DEVCFG_CTRL_PCAP_MODE (1<<26)
143 #define ZY7_DEVCFG_CTRL_QTR_PCAP_RATE_EN (1<<25)
144 #define ZY7_DEVCFG_CTRL_MULTIBOOT_EN (1<<24)
145 #define ZY7_DEVCFG_CTRL_JTAG_CHAIN_DIS (1<<23)
146 #define ZY7_DEVCFG_CTRL_USER_MODE (1<<15)
148 #define ZY7_DEVCFG_CTRL_PCFG_AES_FUSE (1<<12)
149 #define ZY7_DEVCFG_CTRL_PCFG_AES_EN_MASK (7<<9) /* all 1's or 0's */
150 #define ZY7_DEVCFG_CTRL_SEU_EN (1<<8)
151 #define ZY7_DEVCFG_CTRL_SEC_EN (1<<7)
152 #define ZY7_DEVCFG_CTRL_SPNIDEN (1<<6)
153 #define ZY7_DEVCFG_CTRL_SPIDEN (1<<5)
154 #define ZY7_DEVCFG_CTRL_NIDEN (1<<4)
155 #define ZY7_DEVCFG_CTRL_DBGEN (1<<3)
156 #define ZY7_DEVCFG_CTRL_DAP_EN_MASK (7<<0) /* all 1's to enable */
159 #define ZY7_DEVCFG_LOCK_AES_FUSE_LOCK (1<<4)
160 #define ZY7_DEVCFG_LOCK_AES_EN (1<<3)
161 #define ZY7_DEVCFG_LOCK_SEU_LOCK (1<<2)
162 #define ZY7_DEVCFG_LOCK_SEC_LOCK (1<<1)
163 #define ZY7_DEVCFG_LOCK_DBG_LOCK (1<<0)
168 #define ZY7_DEVCFG_CFG_RCLK_EDGE (1<<7)
169 #define ZY7_DEVCFG_CFG_WCLK_EDGE (1<<6)
170 #define ZY7_DEVCFG_CFG_DIS_SRC_INC (1<<5)
171 #define ZY7_DEVCFG_CFG_DIS_DST_INC (1<<4)
175 #define ZY7_DEVCFG_INT_PSS_GTS_USR_B (1<<31)
176 #define ZY7_DEVCFG_INT_PSS_FST_CFG_B (1<<30)
177 #define ZY7_DEVCFG_INT_PSS_GPWRDWN_B (1<<29)
178 #define ZY7_DEVCFG_INT_PSS_GTS_CFG_B (1<<28)
179 #define ZY7_DEVCFG_INT_CFG_RESET_B (1<<27)
180 #define ZY7_DEVCFG_INT_AXI_WTO (1<<23) /* axi write timeout */
181 #define ZY7_DEVCFG_INT_AXI_WERR (1<<22) /* axi write err */
182 #define ZY7_DEVCFG_INT_AXI_RTO (1<<21) /* axi read timeout */
183 #define ZY7_DEVCFG_INT_AXI_RERR (1<<20) /* axi read err */
184 #define ZY7_DEVCFG_INT_RX_FIFO_OV (1<<18) /* rx fifo overflow */
185 #define ZY7_DEVCFG_INT_WR_FIFO_LVL (1<<17) /* wr fifo < level */
186 #define ZY7_DEVCFG_INT_RD_FIFO_LVL (1<<16) /* rd fifo >= level */
187 #define ZY7_DEVCFG_INT_DMA_CMD_ERR (1<<15)
188 #define ZY7_DEVCFG_INT_DMA_Q_OV (1<<14)
189 #define ZY7_DEVCFG_INT_DMA_DONE (1<<13)
190 #define ZY7_DEVCFG_INT_DMA_PCAP_DONE (1<<12)
191 #define ZY7_DEVCFG_INT_P2D_LEN_ERR (1<<11)
192 #define ZY7_DEVCFG_INT_PCFG_HMAC_ERR (1<<6)
193 #define ZY7_DEVCFG_INT_PCFG_SEU_ERR (1<<5)
194 #define ZY7_DEVCFG_INT_PCFG_POR_B (1<<4)
195 #define ZY7_DEVCFG_INT_PCFG_CFG_RST (1<<3)
196 #define ZY7_DEVCFG_INT_PCFG_DONE (1<<2)
197 #define ZY7_DEVCFG_INT_PCFG_INIT_PE (1<<1)
198 #define ZY7_DEVCFG_INT_PCFG_INIT_NE (1<<0)
203 #define ZY7_DEVCFG_STATUS_DMA_CMD_Q_F (1<<31) /* cmd queue full */
204 #define ZY7_DEVCFG_STATUS_DMA_CMD_Q_E (1<<30) /* cmd queue empty */
211 #define ZY7_DEVCFG_STATUS_PSS_GTS_USR_B (1<<11)
212 #define ZY7_DEVCFG_STATUS_PSS_FST_CFG_B (1<<10)
213 #define ZY7_DEVCFG_STATUS_PSS_GPWRDWN_B (1<<9)
214 #define ZY7_DEVCFG_STATUS_PSS_GTS_CFG_B (1<<8)
215 #define ZY7_DEVCFG_STATUS_ILL_APB_ACCE (1<<6)
216 #define ZY7_DEVCFG_STATUS_PSS_CFG_RESET_B (1<<5)
217 #define ZY7_DEVCFG_STATUS_PCFG_INIT (1<<4)
218 #define ZY7_DEVCFG_STATUS_EFUSE_BBRAM_KEY_DIS (1<<3)
219 #define ZY7_DEVCFG_STATUS_EFUSE_SEC_EN (1<<2)
220 #define ZY7_DEVCFG_STATUS_EFUSE_JTAG_DIS (1<<1)
224 #define ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP 1
227 #define ZY7_DEVCFG_DMA_SRC_LEN 0x020 /* in 4-byte words. */
238 #define ZY7_DEVCFG_MCTRL_PCFG_POR_B (1<<8)
239 #define ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK (1<<4)
259 switch (cfg->source) {
276 if (error != 0 || req->newptr == NULL)
280 cfg->source = ZY7_PL_FCLK_SRC_IO;
282 cfg->source = ZY7_PL_FCLK_SRC_DDR;
284 cfg->source = ZY7_PL_FCLK_SRC_ARM;
288 zy7_pl_fclk_set_source(unit, cfg->source);
289 if (cfg->frequency > 0)
290 cfg->actual_frequency = zy7_pl_fclk_get_freq(unit);
307 freq = cfg->frequency;
310 if (error != 0 || req->newptr == NULL)
325 cfg->frequency = freq;
326 cfg->actual_frequency = new_actual_freq;
339 if (error != 0 || req->newptr == NULL)
357 sysctl_ctx_init(&sc->sysctl_tree);
358 sc->sysctl_tree_top = SYSCTL_ADD_NODE(&sc->sysctl_tree,
361 if (sc->sysctl_tree_top == NULL) {
362 sysctl_ctx_free(&sc->sysctl_tree);
363 return (-1);
368 fclk_node = SYSCTL_ADD_NODE(&sc->sysctl_tree,
369 SYSCTL_CHILDREN(sc->sysctl_tree_top), OID_AUTO, fclk_num,
372 SYSCTL_ADD_INT(&sc->sysctl_tree,
377 SYSCTL_ADD_PROC(&sc->sysctl_tree,
383 SYSCTL_ADD_PROC(&sc->sysctl_tree,
401 /* Set devcfg control register. */
449 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i1", hz);
479 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i2", hz);
493 if (!error && nsegs == 1)
500 struct zy7_devcfg_softc *sc = dev->si_drv1;
504 if (sc->is_open) {
509 sc->dma_map = NULL;
510 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 4, 0,
515 1,
519 &sc->sc_mtx,
520 &sc->dma_tag);
526 sc->is_open = 1;
534 struct zy7_devcfg_softc *sc = dev->si_drv1;
542 if (uio->uio_offset == 0 && uio->uio_resid > 0) {
553 err = bus_dmamem_alloc(sc->dma_tag, &dma_mem, BUS_DMA_NOWAIT,
554 &sc->dma_map);
559 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, dma_mem, PAGE_SIZE,
562 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map);
567 while (uio->uio_resid > 0) {
576 segsz = MIN(PAGE_SIZE, uio->uio_resid);
584 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
587 /* Program devcfg's DMA engine. The ordering of these
590 if (uio->uio_resid > segsz)
606 err = mtx_sleep(sc->dma_map, &sc->sc_mtx, PCATCH,
611 bus_dmamap_sync(sc->dma_tag, sc->dma_map,
620 bus_dmamap_unload(sc->dma_tag, sc->dma_map);
621 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map);
629 struct zy7_devcfg_softc *sc = dev->si_drv1;
632 sc->is_open = 0;
633 bus_dma_tag_destroy(sc->dma_tag);
662 wakeup(sc->dma_map);
702 device_set_desc(dev, "Zynq devcfg block");
719 sc->dev = dev;
725 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
727 if (sc->mem_res == NULL) {
735 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
737 if (sc->irq_res == NULL) {
744 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
745 NULL, zy7_devcfg_intr, sc, &sc->intrhandle);
752 /* Create /dev/devcfg */
753 sc->sc_ctl_dev = make_dev(&zy7_devcfg_cdevsw, 0,
754 UID_ROOT, GID_WHEEL, 0600, "devcfg");
755 if (sc->sc_ctl_dev == NULL) {
756 device_printf(dev, "failed to create /dev/devcfg");
760 sc->sc_ctl_dev->si_drv1 = sc;
764 /* Unlock devcfg registers. */
800 if (sc->sysctl_tree_top != NULL) {
801 sysctl_ctx_free(&sc->sysctl_tree);
802 sc->sysctl_tree_top = NULL;
806 if (sc->sc_ctl_dev != NULL)
807 destroy_dev(sc->sc_ctl_dev);
810 if (sc->irq_res != NULL) {
811 if (sc->intrhandle)
812 bus_teardown_intr(dev, sc->irq_res, sc->intrhandle);
814 rman_get_rid(sc->irq_res), sc->irq_res);
818 if (sc->mem_res != NULL)
820 rman_get_rid(sc->mem_res), sc->mem_res);
845 MODULE_DEPEND(zy7_devcfg, zy7_slcr, 1, 1, 1);