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/freebsd-src/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
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/freebsd-src/sys/contrib/device-tree/Bindings/dma/xilinx/
H A Dxilinx_dma.txt11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
24 - #dma-cells: Should be <1>, see "dmas" property below
25 - reg: Should contain VDMA registers location and length.
26 - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
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/freebsd-src/sys/dev/gem/
H A Dif_gemreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 /* Note: Reading the status reg clears bits 0-6. */
45 /* Bits in GEM_SEB register */
49 /* Bits in GEM_CONFIG register */
63 /* Top part of GEM_STATUS has TX completion information */
64 #define GEM_STATUS_TX_COMPLETION_MASK 0xfff80000 /* TX completion reg. */
68 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs
69 * Bits 0-6 auto-clear when read.
71 #define GEM_INTR_TX_INTME 0x00000001 /* Frame w/INTME bit set sent */
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H A Dif_gem.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 2001-2003 Thomas Moestl
42 #if 0 /* XXX: In case of emergency, re-enable this. */
151 device_printf(sc->sc_dev, "flags=0x%x\n", sc->sc_flags); in gem_attach()
154 ifp = sc->sc_if in gem_attach()
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/freebsd-src/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
61 /* *INDENT-OFF* */
65 /* *INDENT-ON* */
97 #define AL_ETH_TSO_MSS_MAX_VAL (AL_ETH_MAX_FRAME_LEN - 200)
174 /** Tx to Rx switching decision type */
182 /** Tx to Rx VLAN ID selection type */
194 * will be set according to inner packet when packet is tunneled, for non-tunneled
268 al_bool obay_enable; /**< stop tx when pause received */
278 * if prio_q_map[1][7] = 0xC, then TX queues 2
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/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8650.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-binding
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H A Dsm8550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-binding
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/freebsd-src/sys/dev/iwm/
H A Dif_iwmreg.h10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
73 * BEGIN iwl-csr.h
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
109 * 31-16: Reserved
110 * 15-
3721 struct iwm_statistics_tx tx; global() member
5248 struct iwm_tx_cmd tx; global() member
5252 struct ieee80211_frame frame[0]; global() member
5405 uint16_t delay; global() member
5571 uint32_t delay; global() member
5882 uint16_t delay; global() member
5901 uint16_t delay; global() member
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/freebsd-src/sys/dev/dc/
H A Dif_dc.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
60 * worth noting is that its multicast hash table is only 128 bits wide
179 "Compex RL100-T
1733 dc_read_srom(struct dc_softc * sc,int bits) dc_read_srom() argument
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/freebsd-src/sys/dev/e1000/
H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
72 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
133 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
145 /* mask to determine if packets should be dropped due to frame errors */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
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/freebsd-src/sys/dev/rl/
H A Dif_rl.c1 /*-
16 * 4. Neither the name of the author nor the names of any co-contributors
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
50 * gains that bus-master DMA usually offers.
52 * For transmission, the chip offers a series of four TX descriptor
53 * registers. Each transmit frame must be in a contiguous buffer, aligned
54 * on a longword (32-bit) boundary. This means we almost always have to
55 * do mbuf copies in order to transmit a frame, except in the unlikely
57 * is 32-bit aligned within the mbuf's data area. The presence of only
72 * On the bright side, the 8139 does have a built-i
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/freebsd-src/sys/dev/stge/
H A Dif_stge.c3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
97 "Sundance ST-1023 Gigabit Ethernet" },
100 "Sundance ST-2021 Gigabit Ethernet" },
119 "D-Link DL-4000 Gigabit Ethernet" },
187 * MII bit-ban
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/freebsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
42 #define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words
43 #define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
62 /* Tx DMA Descriptor Pointer Threshold register */
75 /* Mac Tx Interrupt mitigation threshold */
98 /* MAC Tx DMA size config register */
109 #define AR_FTRIG 0x000003F0 // Mask for Frame trigger level
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/freebsd-src/sys/dev/jme/
H A Dif_jme.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
195 { -1, 0, 0 }
200 { -1, 0, 0 }
205 { -1, 0, 0 }
221 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) in jme_miibus_readreg()
226 for (i = JME_PHY_TIMEOUT; i > 0; i- in jme_miibus_readreg()
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/freebsd-src/sys/dev/vr/
H A Dif_vr.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
40 * and Rhine II PCI controllers, including the D-Link DFE530TX.
52 * receiver has a one entry perfect filter and a 64-bit hash table
107 /* Define to show Rx/Tx error status. */
252 DELAY( in vr_miibus_readreg()
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/freebsd-src/contrib/wpa/src/common/
H A Dqca-vendor.h3 * Copyright (c) 2014-2017, Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2020, The Linux Foundation
5 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc.
28 * enum qca_radiotap_vendor_ids - QCA radiotap vendor namespace IDs
35 * DOC: TX/RX NSS and chain configurations
38 * spatial streams (NSS) and the number of chains used for transmitting (TX) and
41 * Global NSS configuration - Applies to all bands (2.4 GHz and 5/6 GHz)
48 * multiplexing power save frame. The updated NSS value after the connection
62 * Per band NSS configuration - Applies to the 2.4 GHz or 5/6 GHz band
79 * Global chain configuration - Applie
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/freebsd-src/sys/dev/alc/
H A Dif_alc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
98 * enable MSI-X in alc_attach() depending on the card type. The operator can
248 nitems(alc_ident_table) - 1);
253 { -1, 0, 0 }
258 { -1, 0, 0 }
263 { -
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/freebsd-src/sys/dev/msk/
H A Dif_msk.c17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-
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/freebsd-src/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
57 …/Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (…
73 … Mask memory read Bit3 : Mask memory write Bit2 : Mask Completion Bit1 : Mask TX Bit0 : Mask RX
76 … 0x003824UL //Access:R DataWidth:0x20 // tx number of tlp sent
78 …bits for ECO. Bit 0 - For ending "endless completion". 0 - When receiving a completion timeout whi…
79 …dth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header syn…
80 …DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo …
81 …h:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header syn…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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/freebsd-src/sys/dev/ath/
H A Dif_ath_rx.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
44 * by the driver - eg, calls to ath_hal_gettsf32().
134 * NB: older hal's add rx filter bits out of sight and we need to
139 * - when in monitor mode
140 * - if interface marked PROMISC (assumes bridge setting is filtered)
142 * - when operating in station mode for collecting rssi data when
144 * - when operating in adhoc mode so the 802.11 layer creates
146 * - when scanning
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/freebsd-src/sys/dev/age/
H A Dif_age.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
185 { -1, 0, 0 }
190 { -1, 0, 0 }
195 { -1, 0, 0 }
200 { -1, 0, 0 }
217 for (i = AGE_PHY_TIMEOUT; i > 0; i- in age_miibus_readreg()
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/freebsd-src/sys/dev/cadence/
H A Dif_cgem.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com>
31 * interface such as the one used in Xilinx Zynq-7000 SoC.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
96 #define TX_MAX_DMA_SEGS 8 /* maximum segs in a tx mbuf dma */
106 { "cdns,zynq-ge
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/freebsd-src/sys/contrib/dev/iwlwifi/mvm/
H A Dmac80211.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
25 #include "iwl-dr
4429 u32 req_dur, delay; iwl_mvm_send_aux_roc_cmd() local
6058 iwl_mvm_sync_rx_queues_internal(struct iwl_mvm * mvm,enum iwl_mvm_rxq_notif_type type,bool sync,const void * data,u32 size) iwl_mvm_sync_rx_queues_internal() argument
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/freebsd-src/sys/dev/ixgbe/
H A Dixgbe_type.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * - IXGBE_ERROR_INVALID_STATE
48 * - IXGBE_ERROR_POLLING
53 * - IXGBE_ERROR_CAUTION
58 * - IXGBE_ERROR_SOFTWARE
64 * - IXGBE_ERROR_ARGUMEN
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/freebsd-src/sys/dev/usb/controller/
H A Duss820dci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
82 USS820_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
200 if (!sc->sc_flags.d_pulled_up && in uss820dci_pull_up()
201 sc->sc_flags.port_powered) { in uss820dci_pull_up()
202 sc->sc_flags.d_pulled_up = 1; in uss820dci_pull_up()
219 if (sc->sc_flags.d_pulled_up) { in uss820dci_pull_down()
220 sc->sc_flags.d_pulled_up = 0; in uss820dci_pull_down()
233 if (!(sc->sc_flags.status_suspend)) { in uss820dci_wakeup_peer()
256 USS820_WRITE_1(sc, USS820_EPINDEX, td->ep_index); in uss820dci_setup_rx()
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