Lines Matching +full:tx +full:- +full:frame +full:- +full:sync +full:- +full:delay +full:- +full:bits
17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
81 /*-
171 "SK-9Sxx Gigabit Ethernet" },
173 "SK-9Exx Gigabit Ethernet"},
233 "D-Link 550SX Gigabit Ethernet" },
235 "D-Link 560SX Gigabit Ethernet" },
237 "D-Link 560T Gigabit Ethernet" }
378 { -1, 0, 0 }
383 { -1, 0, 0 }
388 { -1, 0, 0 }
393 { -1, 0, 0 }
412 sc = sc_if->msk_softc;
414 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
418 DELAY(1);
419 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
421 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
427 if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
450 sc = sc_if->msk_softc;
452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
453 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
456 DELAY(1);
457 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
462 if_printf(sc_if->msk_ifp, "phy write timeout\n");
477 sc = sc_if->msk_softc;
481 mii = device_get_softc(sc_if->msk_miibus);
482 ifp = sc_if->msk_ifp;
487 sc_if->msk_flags &= ~MSK_FLAG_LINK;
488 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
490 switch (IFM_SUBTYPE(mii->mii_media_active)) {
493 sc_if->msk_flags |= MSK_FLAG_LINK;
499 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0)
500 sc_if->msk_flags |= MSK_FLAG_LINK;
507 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
508 /* Enable Tx FIFO Underrun. */
509 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
514 * speed/flow-control/duplex updates.
517 switch (IFM_SUBTYPE(mii->mii_media_active)) {
529 if ((IFM_OPTIONS(mii->mii_media_active) &
532 if ((IFM_OPTIONS(mii->mii_media_active) &
535 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
540 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
542 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
544 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
545 if ((IFM_OPTIONS(mii->mii_media_active) &
549 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
560 /* Disable Rx/Tx MAC. */
561 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
564 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
566 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
578 /* Just want the 6 least significant bits. */
594 sc = sc_if->msk_softc;
598 ifp = sc_if->msk_ifp;
601 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
631 sc = sc_if->msk_softc;
633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
651 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
652 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
654 for (i = 100; i > 0; i--) {
655 DELAY(100);
656 idx = CSR_READ_2(sc_if->msk_softc,
657 Y2_PREF_Q_ADDR(sc_if->msk_rxq,
663 device_printf(sc_if->msk_if_dev,
675 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
676 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
681 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
682 sc_if->msk_cdata.msk_rx_ring_map,
685 sc_if->msk_cdata.msk_rx_prod = 0;
686 CSR_WRITE_2(sc_if->msk_softc,
687 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
688 sc_if->msk_cdata.msk_rx_prod);
702 sc_if->msk_cdata.msk_rx_cons = 0;
703 sc_if->msk_cdata.msk_rx_prod = 0;
704 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
706 rd = &sc_if->msk_rdata;
707 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
709 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
710 rxd->rx_m = NULL;
711 rxd->rx_le = &rd->msk_rx_ring[prod];
717 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
718 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
720 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
721 rxd->rx_m = NULL;
722 rxd->rx_le = &rd->msk_rx_ring[prod];
723 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
725 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
727 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
729 rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
730 rxd->rx_m = NULL;
731 rxd->rx_le = &rd->msk_rx_ring[prod];
732 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
734 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
736 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
737 nbuf--;
745 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
746 sc_if->msk_cdata.msk_rx_ring_map,
750 sc_if->msk_cdata.msk_rx_prod = prod;
751 CSR_WRITE_2(sc_if->msk_softc,
752 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
753 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) %
769 sc_if->msk_cdata.msk_rx_cons = 0;
770 sc_if->msk_cdata.msk_rx_prod = 0;
771 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
773 rd = &sc_if->msk_rdata;
774 bzero(rd->msk_jumbo_rx_ring,
777 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
778 rxd->rx_m = NULL;
779 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
785 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
786 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) {
788 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
789 rxd->rx_m = NULL;
790 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
791 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
793 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
795 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
797 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
798 rxd->rx_m = NULL;
799 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
800 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
802 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
804 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
805 nbuf--;
813 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
814 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
818 sc_if->msk_cdata.msk_rx_prod = prod;
819 CSR_WRITE_2(sc_if->msk_softc,
820 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
821 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) %
835 sc_if->msk_cdata.msk_tso_mtu = 0;
836 sc_if->msk_cdata.msk_last_csum = 0;
837 sc_if->msk_cdata.msk_tx_prod = 0;
838 sc_if->msk_cdata.msk_tx_cons = 0;
839 sc_if->msk_cdata.msk_tx_cnt = 0;
840 sc_if->msk_cdata.msk_tx_high_addr = 0;
842 rd = &sc_if->msk_rdata;
843 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
845 txd = &sc_if->msk_cdata.msk_txdesc[i];
846 txd->tx_m = NULL;
847 txd->tx_le = &rd->msk_tx_ring[i];
850 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
851 sc_if->msk_cdata.msk_tx_ring_map,
863 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
864 rx_le = rxd->rx_le;
865 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
868 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
869 m = rxd->rx_m;
870 rx_le = rxd->rx_le;
871 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
882 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
883 rx_le = rxd->rx_le;
884 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
887 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
888 m = rxd->rx_m;
889 rx_le = rxd->rx_le;
890 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
907 m->m_len = m->m_pkthdr.len = MCLBYTES;
908 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
915 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
916 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
923 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
925 rx_le = rxd->rx_le;
926 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
927 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
929 rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
931 if (rxd->rx_m != NULL) {
932 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
934 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
935 rxd->rx_m = NULL;
937 map = rxd->rx_dmamap;
938 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
939 sc_if->msk_cdata.msk_rx_sparemap = map;
940 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
942 rxd->rx_m = m;
943 rx_le = rxd->rx_le;
944 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
945 rx_le->msk_control =
964 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
965 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
972 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
973 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
980 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
982 rx_le = rxd->rx_le;
983 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
984 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
986 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
988 if (rxd->rx_m != NULL) {
989 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
990 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
991 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
992 rxd->rx_dmamap);
993 rxd->rx_m = NULL;
995 map = rxd->rx_dmamap;
996 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
997 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
998 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
1000 rxd->rx_m = m;
1001 rx_le = rxd->rx_le;
1002 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
1003 rx_le->msk_control =
1022 mii = device_get_softc(sc_if->msk_miibus);
1044 mii = device_get_softc(sc_if->msk_miibus);
1047 ifmr->ifm_active = mii->mii_media_active;
1048 ifmr->ifm_status = mii->mii_media_status;
1067 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
1069 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1070 if (ifr->ifr_mtu > ETHERMTU) {
1071 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
1076 if ((sc_if->msk_flags &
1085 if_setmtu(ifp, ifr->ifr_mtu);
1097 ((if_getflags(ifp) ^ sc_if->msk_if_flags) &
1100 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0)
1104 sc_if->msk_if_flags = if_getflags(ifp);
1116 mii = device_get_softc(sc_if->msk_miibus);
1117 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1122 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1134 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1160 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
1190 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
1191 device_set_desc(dev, mp->msk_name);
1206 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
1208 device_printf(sc->msk_dev,
1209 "RAM buffer size : %dKB\n", sc->msk_ramsize);
1210 if (sc->msk_ramsize == 0)
1213 sc->msk_pflags |= MSK_FLAG_RAMBUF;
1216 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple
1219 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
1220 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
1221 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
1222 sc->msk_rxqstart[i] = next;
1223 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
1224 next = sc->msk_rxqend[i] + 1;
1225 sc->msk_txqstart[i] = next;
1226 sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
1227 next = sc->msk_txqend[i] + 1;
1229 device_printf(sc->msk_dev,
1231 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
1232 sc->msk_rxqend[i]);
1233 device_printf(sc->msk_dev,
1234 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1235 sc->msk_txqsize / 1024, sc->msk_txqstart[i],
1236 sc->msk_txqend[i]);
1258 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1259 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1260 /* Enable bits are inverted. */
1272 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
1273 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1276 if (sc->msk_num_port > 1)
1280 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
1281 sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1282 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
1287 /* Set all bits to 0 except bits 15..12. */
1306 for (i = 0; i < sc->msk_num_port; i++) {
1316 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1317 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1319 if (sc->msk_num_port > 1)
1327 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1328 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1329 /* Enable bits are inverted. */
1354 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
1355 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
1356 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1357 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
1379 /* Clear all error bits in the PCI status register. */
1380 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1383 pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1388 switch (sc->msk_bustype) {
1394 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1395 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1401 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1403 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1404 if (sc->msk_bustype == MSK_PCIX_BUS) {
1406 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1408 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1416 for (i = 0; i < sc->msk_num_port; i++) {
1424 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1425 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
1431 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR &&
1432 sc->msk_hw_rev > CHIP_REV_YU_SU_B0)
1434 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
1458 if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
1459 sc->msk_hw_id == CHIP_ID_YUKON_EC ||
1460 sc->msk_hw_id == CHIP_ID_YUKON_FE)
1464 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
1500 * On dual port PCI-X card, there is an problem where status
1503 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
1506 pcix_cmd = pci_read_config(sc->msk_dev,
1507 sc->msk_pcixcap + PCIXR_COMMAND, 2);
1511 pci_write_config(sc->msk_dev,
1512 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
1515 if (sc->msk_expcap != 0) {
1517 if (pci_get_max_read_req(sc->msk_dev) == 512)
1518 pci_set_max_read_req(sc->msk_dev, 2048);
1522 bzero(sc->msk_stat_ring,
1523 sizeof(struct msk_stat_desc) * sc->msk_stat_count);
1524 sc->msk_stat_cons = 0;
1525 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1530 addr = sc->msk_stat_ring_paddr;
1534 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1);
1535 if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1536 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1545 if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1546 sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1579 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1580 sc->msk_hw_rev);
1602 port = mmd->port;
1604 sc_if->msk_if_dev = dev;
1605 sc_if->msk_port = port;
1606 sc_if->msk_softc = sc;
1607 sc_if->msk_flags = sc->msk_pflags;
1608 sc->msk_if[port] = sc_if;
1609 /* Setup Tx/Rx queue register offsets. */
1611 sc_if->msk_txq = Q_XA1;
1612 sc_if->msk_txsq = Q_XS1;
1613 sc_if->msk_rxq = Q_R1;
1615 sc_if->msk_txq = Q_XA2;
1616 sc_if->msk_txsq = Q_XS2;
1617 sc_if->msk_rxq = Q_R2;
1620 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1627 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
1636 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
1637 sc->msk_hw_id != CHIP_ID_YUKON_XL)
1639 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1640 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1647 if_setsendqlen(ifp, MSK_TX_RING_CNT - 1);
1671 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) {
1673 * Due to Tx checksum offload hardware bugs, msk(4) manually
1683 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1684 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1692 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1706 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange,
1708 mmd->mii_flags);
1710 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n");
1719 sc->msk_if[port] = NULL;
1738 sc->msk_dev = dev;
1739 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1749 sc->msk_res_spec = msk_res_spec_io;
1751 sc->msk_res_spec = msk_res_spec_mem;
1753 sc->msk_irq_spec = msk_irq_spec_legacy;
1754 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1756 if (sc->msk_res_spec == msk_res_spec_mem)
1757 sc->msk_res_spec = msk_res_spec_io;
1759 sc->msk_res_spec = msk_res_spec_mem;
1760 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1763 sc->msk_res_spec == msk_res_spec_mem ? "memory" :
1765 mtx_destroy(&sc->msk_mtx);
1774 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1775 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1777 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1778 sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1779 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
1781 sc->msk_hw_id, sc->msk_hw_rev);
1782 mtx_destroy(&sc->msk_mtx);
1790 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
1793 sc->msk_process_limit = MSK_PROC_DEFAULT;
1795 "process_limit", &sc->msk_process_limit);
1797 if (sc->msk_process_limit < MSK_PROC_MIN ||
1798 sc->msk_process_limit > MSK_PROC_MAX) {
1801 sc->msk_process_limit = MSK_PROC_DEFAULT;
1805 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
1808 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0,
1809 "Maximum number of time to delay interrupts");
1811 "int_holdoff", &sc->msk_int_holdoff);
1813 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1815 sc->msk_num_port = 1;
1819 sc->msk_num_port++;
1823 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) {
1824 sc->msk_bustype = MSK_PEX_BUS;
1825 sc->msk_expcap = reg;
1826 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) {
1827 sc->msk_bustype = MSK_PCIX_BUS;
1828 sc->msk_pcixcap = reg;
1830 sc->msk_bustype = MSK_PCI_BUS;
1832 switch (sc->msk_hw_id) {
1834 sc->msk_clock = 125; /* 125 MHz */
1835 sc->msk_pflags |= MSK_FLAG_JUMBO;
1838 sc->msk_clock = 125; /* 125 MHz */
1839 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
1842 sc->msk_clock = 125; /* 125 MHz */
1843 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1847 * automatic Tx checksum calculation capability.
1849 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
1850 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
1852 * Yukon Extreme A0 could not use store-and-forward
1853 * for jumbo frames, so disable Tx checksum
1856 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
1857 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
1860 sc->msk_clock = 100; /* 100 MHz */
1861 sc->msk_pflags |= MSK_FLAG_FASTETHER;
1864 sc->msk_clock = 50; /* 50 MHz */
1865 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 |
1867 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1871 * does not rely on status word of received frame
1873 * hardware assistance bits reported by the status
1874 * word as well as validity of the received frame.
1878 sc->msk_pflags |= MSK_FLAG_NOHWVLAN |
1883 sc->msk_clock = 156; /* 156 MHz */
1884 sc->msk_pflags |= MSK_FLAG_JUMBO;
1887 sc->msk_clock = 125; /* 125 MHz */
1888 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1892 sc->msk_clock = 125; /* 125 MHz */
1893 sc->msk_pflags |= MSK_FLAG_JUMBO;
1896 sc->msk_clock = 125; /* 125 MHz */
1897 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
1900 sc->msk_clock = 156; /* 156 MHz */
1914 sc->msk_pflags |= MSK_FLAG_MSI;
1915 sc->msk_irq_spec = msk_irq_spec_msi;
1921 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1931 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1932 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1941 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", DEVICE_UNIT_ANY);
1942 if (sc->msk_devs[MSK_PORT_A] == NULL) {
1948 mmd->port = MSK_PORT_A;
1949 mmd->pmd = sc->msk_pmd;
1950 mmd->mii_flags |= MIIF_DOPAUSE;
1951 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1952 mmd->mii_flags |= MIIF_HAVEFIBER;
1953 if (sc->msk_pmd == 'P')
1954 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1955 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
1957 if (sc->msk_num_port > 1) {
1958 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", DEVICE_UNIT_ANY);
1959 if (sc->msk_devs[MSK_PORT_B] == NULL) {
1966 mmd->port = MSK_PORT_B;
1967 mmd->pmd = sc->msk_pmd;
1968 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1969 mmd->mii_flags |= MIIF_HAVEFIBER;
1970 if (sc->msk_pmd == 'P')
1971 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1972 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
1978 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1979 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand);
2006 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
2010 ifp = sc_if->msk_ifp;
2013 sc_if->msk_flags |= MSK_FLAG_DETACH;
2017 callout_drain(&sc_if->msk_tick_ch);
2027 sc = sc_if->msk_softc;
2028 sc->msk_if[sc_if->msk_port] = NULL;
2048 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
2066 if (sc->msk_intrhand) {
2067 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand);
2068 sc->msk_intrhand = NULL;
2070 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
2071 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0)
2073 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
2074 mtx_destroy(&sc->msk_mtx);
2098 ctx->msk_busaddr = segs[0].ds_addr;
2112 * is 4096. For dual-port controllers, the number of status
2118 sc->msk_stat_count = count;
2121 bus_get_dma_tag(sc->msk_dev), /* parent */
2131 &sc->msk_stat_tag);
2133 device_printf(sc->msk_dev,
2139 error = bus_dmamem_alloc(sc->msk_stat_tag,
2140 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
2141 BUS_DMA_ZERO, &sc->msk_stat_map);
2143 device_printf(sc->msk_dev,
2149 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map,
2150 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2152 device_printf(sc->msk_dev,
2156 sc->msk_stat_ring_paddr = ctx.msk_busaddr;
2166 if (sc->msk_stat_tag) {
2167 if (sc->msk_stat_ring_paddr) {
2168 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
2169 sc->msk_stat_ring_paddr = 0;
2171 if (sc->msk_stat_ring) {
2172 bus_dmamem_free(sc->msk_stat_tag,
2173 sc->msk_stat_ring, sc->msk_stat_map);
2174 sc->msk_stat_ring = NULL;
2176 bus_dma_tag_destroy(sc->msk_stat_tag);
2177 sc->msk_stat_tag = NULL;
2192 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */
2202 &sc_if->msk_cdata.msk_parent_tag);
2204 device_printf(sc_if->msk_if_dev,
2208 /* Create tag for Tx ring. */
2209 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2219 &sc_if->msk_cdata.msk_tx_ring_tag);
2221 device_printf(sc_if->msk_if_dev,
2222 "failed to create Tx ring DMA tag\n");
2227 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2237 &sc_if->msk_cdata.msk_rx_ring_tag);
2239 device_printf(sc_if->msk_if_dev,
2244 /* Create tag for Tx buffers. */
2245 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2255 &sc_if->msk_cdata.msk_tx_tag);
2257 device_printf(sc_if->msk_if_dev,
2258 "failed to create Tx DMA tag\n");
2267 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2270 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2280 &sc_if->msk_cdata.msk_rx_tag);
2282 device_printf(sc_if->msk_if_dev,
2287 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
2288 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
2289 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
2290 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
2292 device_printf(sc_if->msk_if_dev,
2293 "failed to allocate DMA'able memory for Tx ring\n");
2298 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
2299 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
2302 device_printf(sc_if->msk_if_dev,
2303 "failed to load DMA'able memory for Tx ring\n");
2306 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
2309 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
2310 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
2311 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
2313 device_printf(sc_if->msk_if_dev,
2319 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
2320 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
2323 device_printf(sc_if->msk_if_dev,
2327 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
2329 /* Create DMA maps for Tx buffers. */
2331 txd = &sc_if->msk_cdata.msk_txdesc[i];
2332 txd->tx_m = NULL;
2333 txd->tx_dmamap = NULL;
2334 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
2335 &txd->tx_dmamap);
2337 device_printf(sc_if->msk_if_dev,
2338 "failed to create Tx dmamap\n");
2343 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2344 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
2345 device_printf(sc_if->msk_if_dev,
2350 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2351 rxd->rx_m = NULL;
2352 rxd->rx_dmamap = NULL;
2353 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2354 &rxd->rx_dmamap);
2356 device_printf(sc_if->msk_if_dev,
2374 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
2375 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2376 device_printf(sc_if->msk_if_dev,
2377 "disabling jumbo frame support\n");
2381 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2391 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2393 device_printf(sc_if->msk_if_dev,
2403 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2406 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2416 &sc_if->msk_cdata.msk_jumbo_rx_tag);
2418 device_printf(sc_if->msk_if_dev,
2424 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2425 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2427 &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2429 device_printf(sc_if->msk_if_dev,
2435 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2436 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2437 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2440 device_printf(sc_if->msk_if_dev,
2444 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2447 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2448 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2449 device_printf(sc_if->msk_if_dev,
2454 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2455 jrxd->rx_m = NULL;
2456 jrxd->rx_dmamap = NULL;
2457 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2458 &jrxd->rx_dmamap);
2460 device_printf(sc_if->msk_if_dev,
2470 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support "
2472 sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2483 /* Tx ring. */
2484 if (sc_if->msk_cdata.msk_tx_ring_tag) {
2485 if (sc_if->msk_rdata.msk_tx_ring_paddr)
2486 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
2487 sc_if->msk_cdata.msk_tx_ring_map);
2488 if (sc_if->msk_rdata.msk_tx_ring)
2489 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
2490 sc_if->msk_rdata.msk_tx_ring,
2491 sc_if->msk_cdata.msk_tx_ring_map);
2492 sc_if->msk_rdata.msk_tx_ring = NULL;
2493 sc_if->msk_rdata.msk_tx_ring_paddr = 0;
2494 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
2495 sc_if->msk_cdata.msk_tx_ring_tag = NULL;
2498 if (sc_if->msk_cdata.msk_rx_ring_tag) {
2499 if (sc_if->msk_rdata.msk_rx_ring_paddr)
2500 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
2501 sc_if->msk_cdata.msk_rx_ring_map);
2502 if (sc_if->msk_rdata.msk_rx_ring)
2503 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
2504 sc_if->msk_rdata.msk_rx_ring,
2505 sc_if->msk_cdata.msk_rx_ring_map);
2506 sc_if->msk_rdata.msk_rx_ring = NULL;
2507 sc_if->msk_rdata.msk_rx_ring_paddr = 0;
2508 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
2509 sc_if->msk_cdata.msk_rx_ring_tag = NULL;
2511 /* Tx buffers. */
2512 if (sc_if->msk_cdata.msk_tx_tag) {
2514 txd = &sc_if->msk_cdata.msk_txdesc[i];
2515 if (txd->tx_dmamap) {
2516 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2517 txd->tx_dmamap);
2518 txd->tx_dmamap = NULL;
2521 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2522 sc_if->msk_cdata.msk_tx_tag = NULL;
2525 if (sc_if->msk_cdata.msk_rx_tag) {
2527 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2528 if (rxd->rx_dmamap) {
2529 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2530 rxd->rx_dmamap);
2531 rxd->rx_dmamap = NULL;
2534 if (sc_if->msk_cdata.msk_rx_sparemap) {
2535 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2536 sc_if->msk_cdata.msk_rx_sparemap);
2537 sc_if->msk_cdata.msk_rx_sparemap = 0;
2539 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2540 sc_if->msk_cdata.msk_rx_tag = NULL;
2542 if (sc_if->msk_cdata.msk_parent_tag) {
2543 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2544 sc_if->msk_cdata.msk_parent_tag = NULL;
2555 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2556 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr)
2557 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2558 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2559 if (sc_if->msk_rdata.msk_jumbo_rx_ring)
2560 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2561 sc_if->msk_rdata.msk_jumbo_rx_ring,
2562 sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2563 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2564 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0;
2565 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2566 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2569 if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2571 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2572 if (jrxd->rx_dmamap) {
2574 sc_if->msk_cdata.msk_jumbo_rx_tag,
2575 jrxd->rx_dmamap);
2576 jrxd->rx_dmamap = NULL;
2579 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2580 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2581 sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2582 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2584 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2585 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2605 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2606 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) ||
2607 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
2608 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) {
2641 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2655 offset += (ip->ip_hl << 2);
2657 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2664 offset += (tcp->th_off << 2);
2665 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2666 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) &&
2667 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2669 * It seems that Yukon II has Tx checksum offload bug
2673 * the frame minimum ethernet frame size didn't work at
2681 * automatic Tx checksum calculation.
2688 *(uint16_t *)(m->m_data + offset +
2689 m->m_pkthdr.csum_data) = in_cksum_skip(m,
2690 m->m_pkthdr.len, offset);
2691 m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2696 prod = sc_if->msk_cdata.msk_tx_prod;
2697 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2699 map = txd->tx_dmamap;
2700 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
2710 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
2726 if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
2727 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2728 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2737 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2738 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2739 tso_mtu = m->m_pkthdr.tso_segsz;
2741 tso_mtu = offset + m->m_pkthdr.tso_segsz;
2742 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
2743 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2744 tx_le->msk_addr = htole32(tso_mtu);
2745 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2746 tx_le->msk_control = htole32(OP_MSS | HW_OWNER);
2748 tx_le->msk_control =
2750 sc_if->msk_cdata.msk_tx_cnt++;
2752 sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
2757 if ((m->m_flags & M_VLANTAG) != 0) {
2759 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2760 tx_le->msk_addr = htole32(0);
2761 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2762 htons(m->m_pkthdr.ether_vtag));
2763 sc_if->msk_cdata.msk_tx_cnt++;
2766 tx_le->msk_control |= htole32(OP_VLAN |
2767 htons(m->m_pkthdr.ether_vtag));
2772 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2773 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0)
2777 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2780 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff;
2783 if (csum != sc_if->msk_cdata.msk_last_csum) {
2784 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2785 tx_le->msk_addr = htole32(csum);
2786 tx_le->msk_control = htole32(1 << 16 |
2788 sc_if->msk_cdata.msk_tx_cnt++;
2790 sc_if->msk_cdata.msk_last_csum = csum;
2797 sc_if->msk_cdata.msk_tx_high_addr) {
2798 sc_if->msk_cdata.msk_tx_high_addr =
2800 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2801 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr));
2802 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2803 sc_if->msk_cdata.msk_tx_cnt++;
2808 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2809 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2811 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2814 tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2816 sc_if->msk_cdata.msk_tx_cnt++;
2820 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2823 sc_if->msk_cdata.msk_tx_high_addr) {
2824 sc_if->msk_cdata.msk_tx_high_addr =
2826 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2827 tx_le->msk_addr =
2829 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2830 sc_if->msk_cdata.msk_tx_cnt++;
2832 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2835 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2836 tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2838 sc_if->msk_cdata.msk_tx_cnt++;
2842 sc_if->msk_cdata.msk_tx_prod = prod;
2845 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2846 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2847 tx_le->msk_control |= htole32(EOP);
2850 tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2851 tx_le->msk_control |= htole32(HW_OWNER);
2853 txd = &sc_if->msk_cdata.msk_txdesc[prod];
2854 map = txd_last->tx_dmamap;
2855 txd_last->tx_dmamap = txd->tx_dmamap;
2856 txd->tx_dmamap = map;
2857 txd->tx_m = m;
2859 /* Sync descriptors. */
2860 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2861 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2862 sc_if->msk_cdata.msk_tx_ring_map,
2890 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0)
2894 sc_if->msk_cdata.msk_tx_cnt <
2895 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2914 * If there's a BPF listener, bounce a copy of this frame
2922 CSR_WRITE_2(sc_if->msk_softc,
2923 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2924 sc_if->msk_cdata.msk_tx_prod);
2927 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
2938 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
2940 ifp = sc_if->msk_ifp;
2941 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) {
2943 if_printf(sc_if->msk_ifp, "watchdog timeout "
2967 for (i = 0; i < sc->msk_num_port; i++) {
2968 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2969 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) &
2971 msk_stop(sc->msk_if[i]);
2990 for (i = 0; i < sc->msk_num_port; i++) {
2991 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
2992 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) &
2994 msk_stop(sc->msk_if[i]);
3007 sc->msk_pflags |= MSK_FLAG_SUSPEND;
3026 for (i = 0; i < sc->msk_num_port; i++) {
3027 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3028 ((if_getflags(sc->msk_if[i]->msk_ifp) & IFF_UP) != 0)) {
3029 if_setdrvflagbits(sc->msk_if[i]->msk_ifp, 0,
3031 msk_init_locked(sc->msk_if[i]);
3034 sc->msk_pflags &= ~MSK_FLAG_SUSPEND;
3049 dst = src - 3;
3051 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3054 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN);
3067 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) {
3069 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3071 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3074 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3076 m->m_pkthdr.csum_data = 0xffff;
3091 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) {
3093 device_printf(sc_if->msk_if_dev,
3097 pktlen = m->m_pkthdr.len;
3101 if (eh->ether_type != htons(ETHERTYPE_IP))
3104 if (ip->ip_v != IPVERSION)
3107 hlen = ip->ip_hl << 2;
3108 pktlen -= sizeof(struct ether_header);
3111 if (ntohs(ip->ip_len) < hlen)
3113 if (ntohs(ip->ip_len) != pktlen)
3115 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
3118 switch (ip->ip_p) {
3127 if (uh->uh_sum == 0)
3133 csum = bswap16(sc_if->msk_csum & 0xFFFF);
3135 len = hlen - sizeof(struct ip);
3138 for (; len > 0; len -= sizeof(uint16_t), opts++) {
3139 temp32 = csum - *opts;
3144 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
3145 m->m_pkthdr.csum_data = csum;
3157 ifp = sc_if->msk_ifp;
3161 cons = sc_if->msk_cdata.msk_rx_cons;
3166 rxlen -= ETHER_VLAN_ENCAP_LEN;
3167 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
3171 * handle this frame.
3178 } else if (len > sc_if->msk_framesize ||
3181 /* Don't count flow-control packet as errors. */
3188 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) %
3191 rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
3193 m = rxd->rx_m;
3200 m->m_pkthdr.rcvif = ifp;
3201 m->m_pkthdr.len = m->m_len = len;
3203 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3212 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3213 m->m_flags |= M_VLANTAG;
3220 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
3221 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
3233 ifp = sc_if->msk_ifp;
3237 cons = sc_if->msk_cdata.msk_rx_cons;
3242 rxlen -= ETHER_VLAN_ENCAP_LEN;
3243 if (len > sc_if->msk_framesize ||
3246 /* Don't count flow-control packet as errors. */
3253 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) %
3256 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
3258 m = jrxd->rx_m;
3265 m->m_pkthdr.rcvif = ifp;
3266 m->m_pkthdr.len = m->m_len = len;
3268 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3277 m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3278 m->m_flags |= M_VLANTAG;
3285 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
3286 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
3300 ifp = sc_if->msk_ifp;
3302 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
3303 sc_if->msk_cdata.msk_tx_ring_map,
3306 * Go through our tx ring and free mbufs for those
3309 cons = sc_if->msk_cdata.msk_tx_cons;
3312 if (sc_if->msk_cdata.msk_tx_cnt <= 0)
3315 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
3316 control = le32toh(cur_tx->msk_control);
3317 sc_if->msk_cdata.msk_tx_cnt--;
3321 txd = &sc_if->msk_cdata.msk_txdesc[cons];
3322 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
3324 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
3327 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
3329 m_freem(txd->tx_m);
3330 txd->tx_m = NULL;
3334 sc_if->msk_cdata.msk_tx_cons = cons;
3335 if (sc_if->msk_cdata.msk_tx_cnt == 0)
3336 sc_if->msk_watchdog_timer = 0;
3337 /* No need to sync LEs as we didn't update LEs. */
3352 mii = device_get_softc(sc_if->msk_miibus);
3355 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0)
3356 msk_miibus_statchg(sc_if->msk_if_dev);
3358 msk_handle_events(sc_if->msk_softc);
3361 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3373 device_printf(sc_if->msk_if_dev,
3383 sc = sc_if->msk_softc;
3384 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3388 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3390 /* GMAC Tx FIFO underrun. */
3392 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3394 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3397 * In case of Tx underrun, we may need to flush/reset
3398 * Tx MAC but that would also require resynchronization
3413 sc = sc_if->msk_softc;
3415 device_printf(sc_if->msk_if_dev,
3418 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3422 device_printf(sc_if->msk_if_dev,
3425 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3429 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3431 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3435 device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3437 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3440 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3442 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3464 device_printf(sc->msk_dev,
3472 device_printf(sc->msk_dev,
3475 device_printf(sc->msk_dev,
3477 /* Reset all bits in the PCI status register. */
3478 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3480 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3501 device_printf(sc->msk_dev,
3513 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3515 sc->msk_intrhwemask);
3525 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3526 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3527 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3528 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3536 sc = sc_if->msk_softc;
3537 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN))
3539 sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3540 sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3544 sc_if->msk_cdata.msk_rx_ring_tag,
3545 sc_if->msk_cdata.msk_rx_ring_map,
3547 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3548 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3560 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX))
3563 /* Sync status LEs. */
3564 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3569 cons = sc->msk_stat_cons;
3571 sd = &sc->msk_stat_ring[cons];
3572 control = le32toh(sd->msk_control);
3576 sd->msk_control = htole32(control);
3577 status = le32toh(sd->msk_status);
3580 sc_if = sc->msk_if[port];
3582 device_printf(sc->msk_dev, "invalid port opcode "
3589 sc_if->msk_vtag = ntohs(len);
3592 sc_if->msk_vtag = ntohs(len);
3595 sc_if->msk_csum = status;
3598 if (!(if_getdrvflags(sc_if->msk_ifp) & IFF_DRV_RUNNING))
3600 if (sc_if->msk_framesize >
3601 (MCLBYTES - MSK_RX_BUF_ALIGN))
3607 * Because there is no way to sync single Rx LE
3608 * put the DMA sync operation off until the end of
3613 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3619 if (sc->msk_if[MSK_PORT_A] != NULL)
3620 msk_txeof(sc->msk_if[MSK_PORT_A],
3622 if (sc->msk_if[MSK_PORT_B] != NULL)
3623 msk_txeof(sc->msk_if[MSK_PORT_B],
3630 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3634 MSK_INC(cons, sc->msk_stat_count);
3635 if (rxprog > sc->msk_process_limit)
3639 sc->msk_stat_cons = cons;
3640 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3644 msk_rxput(sc->msk_if[MSK_PORT_A]);
3646 msk_rxput(sc->msk_if[MSK_PORT_B]);
3648 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3666 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
3667 (status & sc->msk_intrmask) == 0) {
3673 sc_if0 = sc->msk_if[MSK_PORT_A];
3674 sc_if1 = sc->msk_if[MSK_PORT_B];
3677 ifp0 = sc_if0->msk_ifp;
3679 ifp1 = sc_if1->msk_ifp;
3690 device_printf(sc->msk_dev, "Rx descriptor error\n");
3691 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3692 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3696 device_printf(sc->msk_dev, "Tx descriptor error\n");
3697 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3698 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3727 ifp = sc_if->msk_ifp;
3728 sc = sc_if->msk_softc;
3729 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
3730 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
3731 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
3732 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3736 /* Set Tx GMAC FIFO Almost Empty Threshold. */
3738 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3740 /* Disable Store & Forward mode for Tx. */
3741 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3744 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3773 ifp = sc_if->msk_ifp;
3774 sc = sc_if->msk_softc;
3775 mii = device_get_softc(sc_if->msk_miibus);
3781 /* Cancel pending I/O and free all Rx/Tx buffers. */
3785 sc_if->msk_framesize = ETHERMTU;
3787 sc_if->msk_framesize = if_getmtu(ifp);
3788 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3790 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
3796 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3797 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3798 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3799 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
3800 sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
3801 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3806 * Initialize GMAC first such that speed/duplex/flow-control
3809 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
3812 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3818 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3821 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3824 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3827 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3836 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3840 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L,
3842 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M,
3844 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H,
3846 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L,
3848 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M,
3850 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H,
3854 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3855 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3856 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3859 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3860 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3862 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
3863 sc->msk_hw_id == CHIP_ID_YUKON_EX)
3865 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
3870 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
3871 /* Clear flush mask - HW bug. */
3872 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3875 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3884 /* Another magic for Yukon FE+ - From Linux. */
3885 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3886 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
3888 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
3890 /* Configure Tx MAC FIFO. */
3891 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3892 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3893 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3898 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
3900 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3902 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3904 /* Configure store-and-forward for Tx. */
3908 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3909 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
3910 /* Disable dynamic watermark - from Linux. */
3911 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
3913 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3917 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3918 * arbiter as we don't use Sync Tx queue.
3920 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3923 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3928 /* Disable Tx sync Queue. */
3929 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3931 /* Setup Tx Queue Bus Memory Interface. */
3932 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3933 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3934 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3935 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3936 switch (sc->msk_hw_id) {
3938 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3939 /* Fix for Yukon-EC Ultra: set BMU FIFO level */
3940 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3947 * automatic Tx checksum calculation capability.
3949 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
3950 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3956 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3957 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3958 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3959 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3960 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3961 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
3963 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
3966 msk_set_prefetch(sc, sc_if->msk_txq,
3967 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
3972 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
3977 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
3978 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) {
3979 msk_set_prefetch(sc, sc_if->msk_rxq,
3980 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
3981 MSK_JUMBO_RX_RING_CNT - 1);
3984 msk_set_prefetch(sc, sc_if->msk_rxq,
3985 sc_if->msk_rdata.msk_rx_ring_paddr,
3986 MSK_RX_RING_CNT - 1);
3990 device_printf(sc_if->msk_if_dev,
3995 if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
3996 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
3997 /* Disable flushing of non-ASF packets. */
3998 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
4003 if (sc_if->msk_port == MSK_PORT_A) {
4004 sc->msk_intrmask |= Y2_IS_PORT_A;
4005 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
4007 sc->msk_intrmask |= Y2_IS_PORT_B;
4008 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
4011 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
4012 if (sc->msk_int_holdoff > 0) {
4015 MSK_USECS(sc, sc->msk_int_holdoff));
4017 MSK_USECS(sc, sc->msk_int_holdoff));
4021 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4023 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4029 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4032 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
4041 sc = sc_if->msk_softc;
4042 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
4046 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
4047 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
4048 sc->msk_rxqstart[sc_if->msk_port] / 8);
4049 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
4050 sc->msk_rxqend[sc_if->msk_port] / 8);
4051 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
4052 sc->msk_rxqstart[sc_if->msk_port] / 8);
4053 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
4054 sc->msk_rxqstart[sc_if->msk_port] / 8);
4056 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4057 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
4058 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4059 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
4060 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
4061 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
4062 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
4063 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
4066 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
4067 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
4069 /* Setup Tx Queue. */
4070 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
4071 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
4072 sc->msk_txqstart[sc_if->msk_port] / 8);
4073 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
4074 sc->msk_txqend[sc_if->msk_port] / 8);
4075 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
4076 sc->msk_txqstart[sc_if->msk_port] / 8);
4077 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
4078 sc->msk_txqstart[sc_if->msk_port] / 8);
4079 /* Enable Store & Forward for Tx side. */
4080 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
4081 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
4082 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
4122 sc = sc_if->msk_softc;
4123 ifp = sc_if->msk_ifp;
4125 callout_stop(&sc_if->msk_tick_ch);
4126 sc_if->msk_watchdog_timer = 0;
4129 if (sc_if->msk_port == MSK_PORT_A) {
4130 sc->msk_intrmask &= ~Y2_IS_PORT_A;
4131 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
4133 sc->msk_intrmask &= ~Y2_IS_PORT_B;
4134 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
4136 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4138 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4141 /* Disable Tx/Rx MAC. */
4142 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4144 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
4146 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4150 /* Stop Tx BMU. */
4151 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4152 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4155 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4157 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4160 DELAY(1);
4163 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
4164 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4168 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
4173 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
4175 /* Reset the PCI FIFO of the async Tx queue */
4176 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4179 /* Reset the Tx prefetch units. */
4180 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4183 /* Reset the RAM Buffer async Tx queue. */
4184 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
4186 /* Reset Tx MAC FIFO. */
4187 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4189 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4192 * The Rx Stop command will not work for Yukon-2 if the BMU does not
4203 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4205 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4206 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4208 DELAY(1);
4211 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
4212 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4215 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4218 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
4220 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
4222 /* Free Rx and Tx mbufs still in the queues. */
4224 rxd = &sc_if->msk_cdata.msk_rxdesc[i];
4225 if (rxd->rx_m != NULL) {
4226 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
4227 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4228 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
4229 rxd->rx_dmamap);
4230 m_freem(rxd->rx_m);
4231 rxd->rx_m = NULL;
4235 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
4236 if (jrxd->rx_m != NULL) {
4237 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
4238 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4239 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
4240 jrxd->rx_dmamap);
4241 m_freem(jrxd->rx_m);
4242 jrxd->rx_m = NULL;
4246 txd = &sc_if->msk_cdata.msk_txdesc[i];
4247 if (txd->tx_m != NULL) {
4248 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
4249 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4250 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
4251 txd->tx_dmamap);
4252 m_freem(txd->tx_m);
4253 txd->tx_m = NULL;
4261 sc_if->msk_flags &= ~MSK_FLAG_LINK;
4266 * counter clears high 16 bits of the counter such that accessing
4267 * lower 16 bits should be the last operation.
4285 sc = sc_if->msk_softc;
4287 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4288 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4291 (void)MSK_READ_MIB32(sc_if->msk_port, i);
4294 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4307 ifp = sc_if->msk_ifp;
4310 sc = sc_if->msk_softc;
4311 stats = &sc_if->msk_stats;
4313 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4314 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4317 stats->rx_ucast_frames +=
4318 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
4319 stats->rx_bcast_frames +=
4320 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
4321 stats->rx_pause_frames +=
4322 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
4323 stats->rx_mcast_frames +=
4324 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
4325 stats->rx_crc_errs +=
4326 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
4327 stats->rx_good_octets +=
4328 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
4329 stats->rx_bad_octets +=
4330 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
4331 stats->rx_runts +=
4332 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
4333 stats->rx_runt_errs +=
4334 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
4335 stats->rx_pkts_64 +=
4336 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
4337 stats->rx_pkts_65_127 +=
4338 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
4339 stats->rx_pkts_128_255 +=
4340 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
4341 stats->rx_pkts_256_511 +=
4342 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
4343 stats->rx_pkts_512_1023 +=
4344 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
4345 stats->rx_pkts_1024_1518 +=
4346 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
4347 stats->rx_pkts_1519_max +=
4348 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
4349 stats->rx_pkts_too_long +=
4350 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
4351 stats->rx_pkts_jabbers +=
4352 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
4353 stats->rx_fifo_oflows +=
4354 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
4356 /* Tx stats. */
4357 stats->tx_ucast_frames +=
4358 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
4359 stats->tx_bcast_frames +=
4360 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
4361 stats->tx_pause_frames +=
4362 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
4363 stats->tx_mcast_frames +=
4364 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
4365 stats->tx_octets +=
4366 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
4367 stats->tx_pkts_64 +=
4368 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
4369 stats->tx_pkts_65_127 +=
4370 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
4371 stats->tx_pkts_128_255 +=
4372 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
4373 stats->tx_pkts_256_511 +=
4374 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
4375 stats->tx_pkts_512_1023 +=
4376 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
4377 stats->tx_pkts_1024_1518 +=
4378 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
4379 stats->tx_pkts_1519_max +=
4380 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
4381 stats->tx_colls +=
4382 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
4383 stats->tx_late_colls +=
4384 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
4385 stats->tx_excess_colls +=
4386 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
4387 stats->tx_multi_colls +=
4388 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
4389 stats->tx_single_colls +=
4390 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
4391 stats->tx_underflows +=
4392 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
4395 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4407 sc = sc_if->msk_softc;
4409 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
4412 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4428 sc = sc_if->msk_softc;
4430 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
4433 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4461 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
4462 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
4505 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx",
4506 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics");
4558 if (error || !req->newptr)