Lines Matching +full:tx +full:- +full:frame +full:- +full:sync +full:- +full:delay +full:- +full:bits
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
185 { -1, 0, 0 }
190 { -1, 0, 0 }
195 { -1, 0, 0 }
200 { -1, 0, 0 }
217 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
218 DELAY(1);
225 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
247 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
248 DELAY(1);
255 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
269 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
283 mii = device_get_softc(sc->age_miibus);
286 ifmr->ifm_status = mii->mii_media_status;
287 ifmr->ifm_active = mii->mii_media_active;
292 * Set hardware to newly-selected media.
304 mii = device_get_softc(sc->age_miibus);
305 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
324 if (vendor == sp->age_vendorid &&
325 devid == sp->age_deviceid) {
326 device_set_desc(dev, sp->age_name);
347 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
354 for (i = 100; i > 0; i--) {
355 DELAY(1000);
361 device_printf(sc->age_dev,
365 device_printf(sc->age_dev,
371 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
372 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
373 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
374 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
375 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
376 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
387 DELAY(2000);
389 DELAY(2000);
404 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
406 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
408 for (i = 200; i > 0; i--) {
409 DELAY(1000);
410 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
415 DELAY(1000);
416 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
423 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
428 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
432 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
434 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
437 DELAY(1500 * 1000);
438 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
440 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
467 sc->age_dev = dev;
469 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
471 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
472 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
473 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
477 sc->age_res_spec = age_res_spec_mem;
478 sc->age_irq_spec = age_irq_spec_legacy;
479 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
486 sc->age_phyaddr = AGE_PHY_ADDR;
495 sc->age_rev = pci_get_revid(dev);
496 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
500 sc->age_rev);
502 sc->age_chip_rev);
508 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
512 if (sc->age_chip_rev == 0xFFFF) {
513 device_printf(dev,"invalid chip revision : 0x%04x -- "
514 "not initialized?\n", sc->age_chip_rev);
519 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
538 sc->age_flags |= AGE_FLAG_MSIX;
539 sc->age_irq_spec = age_irq_spec_msix;
543 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
549 sc->age_flags |= AGE_FLAG_MSI;
550 sc->age_irq_spec = age_irq_spec_msi;
556 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
564 sc->age_flags |= AGE_FLAG_PCIE;
567 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
570 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
579 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
580 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
592 ifp = sc->age_ifp = if_alloc(IFT_ETHER);
599 if_setsendqlen(ifp, AGE_TX_RING_CNT - 1);
604 sc->age_flags |= AGE_FLAG_PMCAP;
610 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange,
611 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
618 ether_ifattach(ifp, sc->age_eaddr);
629 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
630 taskqueue_thread_enqueue, &sc->age_tq);
631 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
632 device_get_nameunit(sc->age_dev));
634 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
636 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
641 error = bus_setup_intr(dev, sc->age_irq[i],
643 &sc->age_intrhand[i]);
649 taskqueue_free(sc->age_tq);
650 sc->age_tq = NULL;
671 ifp = sc->age_ifp;
674 sc->age_flags |= AGE_FLAG_DETACH;
677 callout_drain(&sc->age_tick_ch);
678 taskqueue_drain(sc->age_tq, &sc->age_int_task);
679 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
683 if (sc->age_tq != NULL) {
684 taskqueue_drain(sc->age_tq, &sc->age_int_task);
685 taskqueue_free(sc->age_tq);
686 sc->age_tq = NULL;
694 sc->age_ifp = NULL;
697 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
699 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
704 if (sc->age_intrhand[i] != NULL) {
705 bus_teardown_intr(dev, sc->age_irq[i],
706 sc->age_intrhand[i]);
707 sc->age_intrhand[i] = NULL;
711 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
712 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
714 bus_release_resources(dev, sc->age_res_spec, sc->age_res);
715 mtx_destroy(&sc->age_mtx);
725 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
726 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
730 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
731 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
733 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I",
737 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
738 error = resource_int_value(device_get_name(sc->age_dev),
739 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
741 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
742 sc->age_int_mod > AGE_IM_TIMER_MAX) {
743 device_printf(sc->age_dev,
746 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
750 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
751 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
753 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I",
757 sc->age_process_limit = AGE_PROC_DEFAULT;
758 error = resource_int_value(device_get_name(sc->age_dev),
759 device_get_unit(sc->age_dev), "process_limit",
760 &sc->age_process_limit);
762 if (sc->age_process_limit < AGE_PROC_MIN ||
763 sc->age_process_limit > AGE_PROC_MAX) {
764 device_printf(sc->age_dev,
767 sc->age_process_limit = AGE_PROC_DEFAULT;
787 ctx->age_busaddr = segs[0].ds_addr;
802 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
803 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
804 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
805 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
806 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
807 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
810 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
812 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
814 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
816 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
818 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
844 bus_get_dma_tag(sc->age_dev), /* parent */
854 &sc->age_cdata.age_parent_tag);
856 device_printf(sc->age_dev,
861 /* Create tag for Tx ring. */
863 sc->age_cdata.age_parent_tag, /* parent */
873 &sc->age_cdata.age_tx_ring_tag);
875 device_printf(sc->age_dev,
876 "could not create Tx ring DMA tag.\n");
882 sc->age_cdata.age_parent_tag, /* parent */
892 &sc->age_cdata.age_rx_ring_tag);
894 device_printf(sc->age_dev,
901 sc->age_cdata.age_parent_tag, /* parent */
911 &sc->age_cdata.age_rr_ring_tag);
913 device_printf(sc->age_dev,
920 sc->age_cdata.age_parent_tag, /* parent */
930 &sc->age_cdata.age_cmb_block_tag);
932 device_printf(sc->age_dev,
939 sc->age_cdata.age_parent_tag, /* parent */
949 &sc->age_cdata.age_smb_block_tag);
951 device_printf(sc->age_dev,
957 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
958 (void **)&sc->age_rdata.age_tx_ring,
960 &sc->age_cdata.age_tx_ring_map);
962 device_printf(sc->age_dev,
963 "could not allocate DMA'able memory for Tx ring.\n");
967 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
968 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
971 device_printf(sc->age_dev,
972 "could not load DMA'able memory for Tx ring.\n");
975 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
977 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
978 (void **)&sc->age_rdata.age_rx_ring,
980 &sc->age_cdata.age_rx_ring_map);
982 device_printf(sc->age_dev,
987 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
988 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
991 device_printf(sc->age_dev,
995 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
997 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
998 (void **)&sc->age_rdata.age_rr_ring,
1000 &sc->age_cdata.age_rr_ring_map);
1002 device_printf(sc->age_dev,
1007 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1008 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1012 device_printf(sc->age_dev,
1016 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1018 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1019 (void **)&sc->age_rdata.age_cmb_block,
1021 &sc->age_cdata.age_cmb_block_map);
1023 device_printf(sc->age_dev,
1028 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1029 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1032 device_printf(sc->age_dev,
1036 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1038 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1039 (void **)&sc->age_rdata.age_smb_block,
1041 &sc->age_cdata.age_smb_block_map);
1043 device_printf(sc->age_dev,
1048 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1049 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1052 device_printf(sc->age_dev,
1056 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1064 device_printf(sc->age_dev, "4GB boundary crossed, "
1073 * Create Tx/Rx buffer parent tag.
1074 * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1081 bus_get_dma_tag(sc->age_dev), /* parent */
1091 &sc->age_cdata.age_buffer_tag);
1093 device_printf(sc->age_dev,
1098 /* Create tag for Tx buffers. */
1100 sc->age_cdata.age_buffer_tag, /* parent */
1110 &sc->age_cdata.age_tx_tag);
1112 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1118 sc->age_cdata.age_buffer_tag, /* parent */
1128 &sc->age_cdata.age_rx_tag);
1130 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1134 /* Create DMA maps for Tx buffers. */
1136 txd = &sc->age_cdata.age_txdesc[i];
1137 txd->tx_m = NULL;
1138 txd->tx_dmamap = NULL;
1139 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1140 &txd->tx_dmamap);
1142 device_printf(sc->age_dev,
1143 "could not create Tx dmamap.\n");
1148 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1149 &sc->age_cdata.age_rx_sparemap)) != 0) {
1150 device_printf(sc->age_dev,
1155 rxd = &sc->age_cdata.age_rxdesc[i];
1156 rxd->rx_m = NULL;
1157 rxd->rx_dmamap = NULL;
1158 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1159 &rxd->rx_dmamap);
1161 device_printf(sc->age_dev,
1178 /* Tx buffers */
1179 if (sc->age_cdata.age_tx_tag != NULL) {
1181 txd = &sc->age_cdata.age_txdesc[i];
1182 if (txd->tx_dmamap != NULL) {
1183 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1184 txd->tx_dmamap);
1185 txd->tx_dmamap = NULL;
1188 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1189 sc->age_cdata.age_tx_tag = NULL;
1192 if (sc->age_cdata.age_rx_tag != NULL) {
1194 rxd = &sc->age_cdata.age_rxdesc[i];
1195 if (rxd->rx_dmamap != NULL) {
1196 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1197 rxd->rx_dmamap);
1198 rxd->rx_dmamap = NULL;
1201 if (sc->age_cdata.age_rx_sparemap != NULL) {
1202 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1203 sc->age_cdata.age_rx_sparemap);
1204 sc->age_cdata.age_rx_sparemap = NULL;
1206 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1207 sc->age_cdata.age_rx_tag = NULL;
1209 /* Tx ring. */
1210 if (sc->age_cdata.age_tx_ring_tag != NULL) {
1211 if (sc->age_rdata.age_tx_ring_paddr != 0)
1212 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1213 sc->age_cdata.age_tx_ring_map);
1214 if (sc->age_rdata.age_tx_ring != NULL)
1215 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1216 sc->age_rdata.age_tx_ring,
1217 sc->age_cdata.age_tx_ring_map);
1218 sc->age_rdata.age_tx_ring_paddr = 0;
1219 sc->age_rdata.age_tx_ring = NULL;
1220 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1221 sc->age_cdata.age_tx_ring_tag = NULL;
1224 if (sc->age_cdata.age_rx_ring_tag != NULL) {
1225 if (sc->age_rdata.age_rx_ring_paddr != 0)
1226 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1227 sc->age_cdata.age_rx_ring_map);
1228 if (sc->age_rdata.age_rx_ring != NULL)
1229 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1230 sc->age_rdata.age_rx_ring,
1231 sc->age_cdata.age_rx_ring_map);
1232 sc->age_rdata.age_rx_ring_paddr = 0;
1233 sc->age_rdata.age_rx_ring = NULL;
1234 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1235 sc->age_cdata.age_rx_ring_tag = NULL;
1238 if (sc->age_cdata.age_rr_ring_tag != NULL) {
1239 if (sc->age_rdata.age_rr_ring_paddr != 0)
1240 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1241 sc->age_cdata.age_rr_ring_map);
1242 if (sc->age_rdata.age_rr_ring != NULL)
1243 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1244 sc->age_rdata.age_rr_ring,
1245 sc->age_cdata.age_rr_ring_map);
1246 sc->age_rdata.age_rr_ring_paddr = 0;
1247 sc->age_rdata.age_rr_ring = NULL;
1248 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1249 sc->age_cdata.age_rr_ring_tag = NULL;
1252 if (sc->age_cdata.age_cmb_block_tag != NULL) {
1253 if (sc->age_rdata.age_cmb_block_paddr != 0)
1254 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1255 sc->age_cdata.age_cmb_block_map);
1256 if (sc->age_rdata.age_cmb_block != NULL)
1257 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1258 sc->age_rdata.age_cmb_block,
1259 sc->age_cdata.age_cmb_block_map);
1260 sc->age_rdata.age_cmb_block_paddr = 0;
1261 sc->age_rdata.age_cmb_block = NULL;
1262 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1263 sc->age_cdata.age_cmb_block_tag = NULL;
1266 if (sc->age_cdata.age_smb_block_tag != NULL) {
1267 if (sc->age_rdata.age_smb_block_paddr != 0)
1268 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1269 sc->age_cdata.age_smb_block_map);
1270 if (sc->age_rdata.age_smb_block != NULL)
1271 bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1272 sc->age_rdata.age_smb_block,
1273 sc->age_cdata.age_smb_block_map);
1274 sc->age_rdata.age_smb_block_paddr = 0;
1275 sc->age_rdata.age_smb_block = NULL;
1276 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1277 sc->age_cdata.age_smb_block_tag = NULL;
1280 if (sc->age_cdata.age_buffer_tag != NULL) {
1281 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1282 sc->age_cdata.age_buffer_tag = NULL;
1284 if (sc->age_cdata.age_parent_tag != NULL) {
1285 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1286 sc->age_cdata.age_parent_tag = NULL;
1311 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1323 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1329 ifp = sc->age_ifp;
1333 * auto-negotiation but we don't know whether that operation
1341 * Save current negotiated media speed/duplex/flow-control
1346 mii = device_get_softc(sc->age_miibus);
1349 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1350 switch IFM_SUBTYPE(mii->mii_media_active) {
1360 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1362 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1365 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1367 DELAY(1000);
1372 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1374 mii->mii_media_active)) {
1388 device_printf(sc->age_dev,
1393 * No link, force MAC to have 100Mbps, full-duplex link.
1396 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1397 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1417 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1421 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1457 ifp = sc->age_ifp;
1488 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1490 * L1 requires offset of TCP/UDP payload in its Tx
1491 * descriptor to perform hardware Tx checksum offload.
1520 * Additional check for LLC/SNAP frame?
1522 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1536 poff = ip_off + (ip->ip_hl << 2);
1537 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1544 m = m_pullup(m, poff + (tcp->th_off << 2));
1565 ip->ip_sum = 0;
1566 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1567 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1572 si = prod = sc->age_cdata.age_tx_prod;
1573 txd = &sc->age_cdata.age_txdesc[prod];
1575 map = txd->tx_dmamap;
1577 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1587 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1603 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1604 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1610 if ((m->m_flags & M_VLANTAG) != 0) {
1611 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1618 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1622 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1625 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1626 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1632 hdrlen = poff + (tcp->th_off << 2);
1633 desc = &sc->age_rdata.age_tx_ring[prod];
1634 desc->addr = htole64(txsegs[0].ds_addr);
1635 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag);
1636 desc->flags = htole32(cflags);
1637 sc->age_cdata.age_tx_cnt++;
1639 if (m->m_len - hdrlen > 0) {
1641 desc = &sc->age_rdata.age_tx_ring[prod];
1642 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
1643 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) |
1645 desc->flags = htole32(cflags);
1646 sc->age_cdata.age_tx_cnt++;
1651 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1652 /* Configure Tx IP/TCP/UDP checksum offload. */
1654 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1656 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1661 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1665 desc = &sc->age_rdata.age_tx_ring[prod];
1666 desc->addr = htole64(txsegs[i].ds_addr);
1667 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1668 desc->flags = htole32(cflags);
1669 sc->age_cdata.age_tx_cnt++;
1673 sc->age_cdata.age_tx_prod = prod;
1676 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1677 desc = &sc->age_rdata.age_tx_ring[prod];
1678 desc->flags |= htole32(AGE_TD_EOP);
1681 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1682 desc = &sc->age_rdata.age_tx_ring[si];
1683 desc->flags |= htole32(AGE_TD_TSO_HDR);
1687 txd = &sc->age_cdata.age_txdesc[prod];
1688 map = txd_last->tx_dmamap;
1689 txd_last->tx_dmamap = txd->tx_dmamap;
1690 txd->tx_dmamap = map;
1691 txd->tx_m = m;
1693 /* Sync descriptors. */
1694 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1695 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1696 sc->age_cdata.age_tx_ring_map,
1725 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0)
1747 * If there's a BPF listener, bounce a copy of this frame
1757 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1768 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1771 ifp = sc->age_ifp;
1772 if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1773 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1779 if (sc->age_cdata.age_tx_cnt == 0) {
1780 if_printf(sc->age_ifp,
1781 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1786 if_printf(sc->age_ifp, "watchdog timeout\n");
1808 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1810 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1812 if_setmtu(ifp, ifr->ifr_mtu);
1824 if (((if_getflags(ifp) ^ sc->age_if_flags)
1828 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1835 sc->age_if_flags = if_getflags(ifp);
1847 mii = device_get_softc(sc->age_miibus);
1848 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1852 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1917 mii = device_get_softc(sc->age_miibus);
1923 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1932 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1935 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1937 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1956 mii = device_get_softc(sc->age_miibus);
1957 ifp = sc->age_ifp;
1964 sc->age_flags &= ~AGE_FLAG_LINK;
1965 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1966 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1970 sc->age_flags |= AGE_FLAG_LINK;
1977 /* Stop Rx/Tx MACs. */
1981 /* Program MACs with resolved speed/duplex/flow-control. */
1982 if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
1985 /* Restart DMA engine and Tx/Rx MAC. */
2004 stat = &sc->age_stat;
2006 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2007 sc->age_cdata.age_smb_block_map,
2010 smb = sc->age_rdata.age_smb_block;
2011 if (smb->updated == 0)
2014 ifp = sc->age_ifp;
2016 stat->rx_frames += smb->rx_frames;
2017 stat->rx_bcast_frames += smb->rx_bcast_frames;
2018 stat->rx_mcast_frames += smb->rx_mcast_frames;
2019 stat->rx_pause_frames += smb->rx_pause_frames;
2020 stat->rx_control_frames += smb->rx_control_frames;
2021 stat->rx_crcerrs += smb->rx_crcerrs;
2022 stat->rx_lenerrs += smb->rx_lenerrs;
2023 stat->rx_bytes += smb->rx_bytes;
2024 stat->rx_runts += smb->rx_runts;
2025 stat->rx_fragments += smb->rx_fragments;
2026 stat->rx_pkts_64 += smb->rx_pkts_64;
2027 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2028 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2029 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2030 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2031 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2032 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2033 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2034 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2035 stat->rx_desc_oflows += smb->rx_desc_oflows;
2036 stat->rx_alignerrs += smb->rx_alignerrs;
2037 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2038 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2039 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2041 /* Tx stats. */
2042 stat->tx_frames += smb->tx_frames;
2043 stat->tx_bcast_frames += smb->tx_bcast_frames;
2044 stat->tx_mcast_frames += smb->tx_mcast_frames;
2045 stat->tx_pause_frames += smb->tx_pause_frames;
2046 stat->tx_excess_defer += smb->tx_excess_defer;
2047 stat->tx_control_frames += smb->tx_control_frames;
2048 stat->tx_deferred += smb->tx_deferred;
2049 stat->tx_bytes += smb->tx_bytes;
2050 stat->tx_pkts_64 += smb->tx_pkts_64;
2051 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2052 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2053 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2054 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2055 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2056 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2057 stat->tx_single_colls += smb->tx_single_colls;
2058 stat->tx_multi_colls += smb->tx_multi_colls;
2059 stat->tx_late_colls += smb->tx_late_colls;
2060 stat->tx_excess_colls += smb->tx_excess_colls;
2061 stat->tx_underrun += smb->tx_underrun;
2062 stat->tx_desc_underrun += smb->tx_desc_underrun;
2063 stat->tx_lenerrs += smb->tx_lenerrs;
2064 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2065 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2066 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2069 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2071 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2072 smb->tx_multi_colls + smb->tx_late_colls +
2073 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2075 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls +
2076 smb->tx_late_colls + smb->tx_underrun +
2077 smb->tx_pkts_truncated);
2079 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2081 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs +
2082 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated +
2083 smb->rx_fifo_oflows + smb->rx_desc_oflows +
2084 smb->rx_alignerrs);
2087 smb->updated = 0;
2089 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2090 sc->age_cdata.age_smb_block_map,
2107 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2124 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2125 sc->age_cdata.age_cmb_block_map,
2127 cmb = sc->age_rdata.age_cmb_block;
2128 status = le32toh(cmb->intr_status);
2129 if (sc->age_morework != 0)
2134 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2136 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2139 cmb->intr_status = 0;
2140 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2141 sc->age_cdata.age_cmb_block_map,
2144 ifp = sc->age_ifp;
2147 sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2148 sc->age_process_limit);
2150 age_txintr(sc, sc->age_tpd_cons);
2153 device_printf(sc->age_dev,
2154 "DMA read error! -- resetting\n");
2156 device_printf(sc->age_dev,
2157 "DMA write error! -- resetting\n");
2167 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2168 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2169 sc->age_cdata.age_cmb_block_map,
2171 status = le32toh(cmb->intr_status);
2172 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2173 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2179 /* Re-enable interrupts. */
2193 ifp = sc->age_ifp;
2195 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2196 sc->age_cdata.age_tx_ring_map,
2200 * Go through our Tx list and free mbufs for those
2203 cons = sc->age_cdata.age_tx_cons;
2205 if (sc->age_cdata.age_tx_cnt <= 0)
2209 sc->age_cdata.age_tx_cnt--;
2210 txd = &sc->age_cdata.age_txdesc[cons];
2212 * Clear Tx descriptors, it's not required but would
2213 * help debugging in case of Tx issues.
2215 txd->tx_desc->addr = 0;
2216 txd->tx_desc->len = 0;
2217 txd->tx_desc->flags = 0;
2219 if (txd->tx_m == NULL)
2222 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2224 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2225 m_freem(txd->tx_m);
2226 txd->tx_m = NULL;
2230 sc->age_cdata.age_tx_cons = cons;
2234 * Tx descriptors in queue.
2236 if (sc->age_cdata.age_tx_cnt == 0)
2237 sc->age_watchdog_timer = 0;
2238 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2239 sc->age_cdata.age_tx_ring_map,
2253 dst = src - 3;
2255 if (m->m_next == NULL) {
2256 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2258 m->m_data -= 6;
2264 * cycles for jumbo frame.
2272 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2273 m->m_data += ETHER_HDR_LEN;
2274 m->m_len -= ETHER_HDR_LEN;
2275 n->m_len = ETHER_HDR_LEN;
2277 n->m_next = m;
2282 /* Receive a frame. */
2295 ifp = sc->age_ifp;
2296 status = le32toh(rxrd->flags);
2297 index = le32toh(rxrd->index);
2301 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2309 * o frame length and protocol specific length
2320 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2321 mp = rxd->rx_m;
2326 if (sc->age_cdata.age_rxhead != NULL)
2327 m_freem(sc->age_cdata.age_rxhead);
2332 * Assume we've received a full sized frame.
2334 * multi-segmented frame.
2336 mp->m_len = AGE_RX_BUF_SIZE;
2339 if (sc->age_cdata.age_rxhead == NULL) {
2340 sc->age_cdata.age_rxhead = mp;
2341 sc->age_cdata.age_rxtail = mp;
2343 mp->m_flags &= ~M_PKTHDR;
2344 sc->age_cdata.age_rxprev_tail =
2345 sc->age_cdata.age_rxtail;
2346 sc->age_cdata.age_rxtail->m_next = mp;
2347 sc->age_cdata.age_rxtail = mp;
2350 if (count == nsegs - 1) {
2351 /* Last desc. for this frame. */
2352 m = sc->age_cdata.age_rxhead;
2353 m->m_flags |= M_PKTHDR;
2358 m->m_pkthdr.len = sc->age_cdata.age_rxlen -
2362 mp->m_len = sc->age_cdata.age_rxlen -
2363 ((nsegs - 1) * AGE_RX_BUF_SIZE);
2365 if (mp->m_len <= ETHER_CRC_LEN) {
2366 sc->age_cdata.age_rxtail =
2367 sc->age_cdata.age_rxprev_tail;
2368 sc->age_cdata.age_rxtail->m_len -=
2369 (ETHER_CRC_LEN - mp->m_len);
2370 sc->age_cdata.age_rxtail->m_next = NULL;
2373 mp->m_len -= ETHER_CRC_LEN;
2376 m->m_len = m->m_pkthdr.len;
2377 m->m_pkthdr.rcvif = ifp;
2393 m->m_pkthdr.csum_flags |=
2397 m->m_pkthdr.csum_flags |=
2399 m->m_pkthdr.csum_data = 0xffff;
2411 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2412 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2413 m->m_flags |= M_VLANTAG;
2440 rr_cons = sc->age_cdata.age_rr_cons;
2444 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2445 sc->age_cdata.age_rr_ring_map,
2447 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2448 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2451 if (count-- <= 0)
2453 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2454 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2459 * Non-matching value would indicate that hardware
2463 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2467 /* Received a frame. */
2470 rxrd->index = 0;
2472 sc->age_cdata.age_rx_cons += nsegs;
2473 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2478 sc->age_cdata.age_rr_cons = rr_cons;
2480 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2481 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
2482 /* Sync descriptors. */
2483 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2484 sc->age_cdata.age_rr_ring_map,
2504 mii = device_get_softc(sc->age_miibus);
2507 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2518 DELAY(1000);
2519 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2522 DELAY(10);
2526 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2556 ifp = sc->age_ifp;
2557 mii = device_get_softc(sc->age_miibus);
2575 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2591 paddr = sc->age_rdata.age_tx_ring_paddr;
2593 paddr = sc->age_rdata.age_rx_ring_paddr;
2595 paddr = sc->age_rdata.age_rr_ring_paddr;
2597 paddr = sc->age_rdata.age_tx_ring_paddr;
2599 paddr = sc->age_rdata.age_cmb_block_paddr;
2601 paddr = sc->age_rdata.age_smb_block_paddr;
2608 /* Set Tx descriptor counter. */
2618 * through this mailbox register. However Tx producer and
2620 * it's hard to separate code path between Tx and Rx without
2622 * for Tx and Rx consumer/producer management we could have
2623 * independent Tx/Rx handler which in turn Rx handler could have
2635 /* Set parameters for half-duplex media. */
2647 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2650 if (AGE_USECS(sc->age_int_mod) == 0)
2656 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2657 sc->age_int_mod);
2660 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2662 sc->age_max_frame_size = ETHERMTU;
2664 sc->age_max_frame_size = if_getmtu(ifp);
2665 sc->age_max_frame_size += ETHER_HDR_LEN +
2667 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2668 /* Configure jumbo frame. */
2669 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2678 /* Configure flow-control parameters. From Linux. */
2679 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2681 * Magic workaround for old-L1.
2686 * Another magic workaround for flow-control mode
2698 switch (sc->age_chip_rev) {
2764 sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2765 sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2783 * Disable all WOL bits as WOL can interfere normal Rx
2789 * Configure Tx/Rx MACs.
2790 * - Auto-padding for short frames.
2791 * - Enable CRC generation.
2792 * Start with full-duplex/1000Mbps media. Actual reconfiguration
2812 /* Finally enable Tx/Rx MAC. */
2815 sc->age_flags &= ~AGE_FLAG_LINK;
2819 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2838 ifp = sc->age_ifp;
2840 sc->age_flags &= ~AGE_FLAG_LINK;
2841 callout_stop(&sc->age_tick_ch);
2842 sc->age_watchdog_timer = 0;
2851 /* Stop Rx/Tx MAC. */
2862 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2865 DELAY(10);
2868 device_printf(sc->age_dev,
2869 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2872 if (sc->age_cdata.age_rxhead != NULL)
2873 m_freem(sc->age_cdata.age_rxhead);
2876 * Free RX and TX mbufs still in the queues.
2879 rxd = &sc->age_cdata.age_rxdesc[i];
2880 if (rxd->rx_m != NULL) {
2881 bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2882 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2883 bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2884 rxd->rx_dmamap);
2885 m_freem(rxd->rx_m);
2886 rxd->rx_m = NULL;
2890 txd = &sc->age_cdata.age_txdesc[i];
2891 if (txd->tx_m != NULL) {
2892 bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2893 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2894 bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2895 txd->tx_dmamap);
2896 m_freem(txd->tx_m);
2897 txd->tx_m = NULL;
2915 /* Stop Tx DMA engine. */
2921 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2925 DELAY(10);
2928 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2950 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2954 DELAY(10);
2957 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2969 sc->age_cdata.age_tx_prod = 0;
2970 sc->age_cdata.age_tx_cons = 0;
2971 sc->age_cdata.age_tx_cnt = 0;
2973 rd = &sc->age_rdata;
2974 bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2976 txd = &sc->age_cdata.age_txdesc[i];
2977 txd->tx_desc = &rd->age_tx_ring[i];
2978 txd->tx_m = NULL;
2981 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2982 sc->age_cdata.age_tx_ring_map,
2995 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
2996 sc->age_morework = 0;
2997 rd = &sc->age_rdata;
2998 bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
3000 rxd = &sc->age_cdata.age_rxdesc[i];
3001 rxd->rx_m = NULL;
3002 rxd->rx_desc = &rd->age_rx_ring[i];
3007 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
3008 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
3020 sc->age_cdata.age_rr_cons = 0;
3023 rd = &sc->age_rdata;
3024 bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3025 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3026 sc->age_cdata.age_rr_ring_map,
3037 rd = &sc->age_rdata;
3038 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3039 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3040 sc->age_cdata.age_cmb_block_map,
3051 rd = &sc->age_rdata;
3052 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3053 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3054 sc->age_cdata.age_smb_block_map,
3072 m->m_len = m->m_pkthdr.len = MCLBYTES;
3077 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3078 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3084 if (rxd->rx_m != NULL) {
3085 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3087 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3089 map = rxd->rx_dmamap;
3090 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3091 sc->age_cdata.age_rx_sparemap = map;
3092 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3094 rxd->rx_m = m;
3096 desc = rxd->rx_desc;
3097 desc->addr = htole64(segs[0].ds_addr);
3098 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3111 ifp = sc->age_ifp;
3140 ifp = sc->age_ifp;
3173 result = -1;
3176 if (error != 0 || req->newptr == NULL)
3183 stats = &sc->age_stat;
3184 printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3186 (uintmax_t)stats->tx_frames);
3188 (uintmax_t)stats->tx_bcast_frames);
3190 (uintmax_t)stats->tx_mcast_frames);
3192 stats->tx_pause_frames);
3194 stats->tx_control_frames);
3196 stats->tx_excess_defer);
3198 stats->tx_deferred);
3200 (uintmax_t)stats->tx_bytes);
3202 (uintmax_t)stats->tx_bcast_bytes);
3204 (uintmax_t)stats->tx_mcast_bytes);
3206 (uintmax_t)stats->tx_pkts_64);
3208 (uintmax_t)stats->tx_pkts_65_127);
3210 (uintmax_t)stats->tx_pkts_128_255);
3212 (uintmax_t)stats->tx_pkts_256_511);
3214 (uintmax_t)stats->tx_pkts_512_1023);
3216 (uintmax_t)stats->tx_pkts_1024_1518);
3218 (uintmax_t)stats->tx_pkts_1519_max);
3220 stats->tx_single_colls);
3222 stats->tx_multi_colls);
3224 stats->tx_late_colls);
3226 stats->tx_excess_colls);
3228 stats->tx_underrun);
3229 printf("Transmit descriptor write-back errors : %u\n",
3230 stats->tx_desc_underrun);
3231 printf("Transmit frames with length mismatched frame size : %u\n",
3232 stats->tx_lenerrs);
3234 stats->tx_lenerrs);
3237 (uintmax_t)stats->rx_frames);
3239 (uintmax_t)stats->rx_bcast_frames);
3241 (uintmax_t)stats->rx_mcast_frames);
3243 stats->rx_pause_frames);
3245 stats->rx_control_frames);
3247 stats->rx_crcerrs);
3249 stats->rx_lenerrs);
3251 (uintmax_t)stats->rx_bytes);
3253 (uintmax_t)stats->rx_bcast_bytes);
3255 (uintmax_t)stats->rx_mcast_bytes);
3257 stats->rx_runts);
3259 (uintmax_t)stats->rx_fragments);
3261 (uintmax_t)stats->rx_pkts_64);
3263 (uintmax_t)stats->rx_pkts_65_127);
3265 (uintmax_t)stats->rx_pkts_128_255);
3267 (uintmax_t)stats->rx_pkts_256_511);
3269 (uintmax_t)stats->rx_pkts_512_1023);
3271 (uintmax_t)stats->rx_pkts_1024_1518);
3273 (uintmax_t)stats->rx_pkts_1519_max);
3275 (uint64_t)stats->rx_pkts_truncated);
3277 stats->rx_fifo_oflows);
3279 stats->rx_desc_oflows);
3281 stats->rx_alignerrs);
3283 (uint64_t)stats->rx_pkts_filtered);
3297 if (error || req->newptr == NULL)