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/llvm-project/polly/lib/External/isl/imath/tests/
H A Dsub.tc3 sub:0,0,0:0
4 sub:0,0,=1:0
5 sub:1,=1,=1:0
6 sub:1,-1,0:2
7 sub:1,-1,=2:2
8 sub:1,-1,=1:2
9 sub:-1,1,0:-2
10 sub:-1,1,=1:-2
12 sub:103427990038,909510006269847,0:-909406578279809
13 sub:128593002,-9007199254740992,0:9007199383333994
[all …]
/llvm-project/llvm/test/MC/X86/apx/
H A Dsub-intel.s3 # CHECK: {evex} sub bl, 123
5 {evex} sub bl, 123
6 # CHECK: {nf} sub bl, 123
8 {nf} sub bl, 123
9 # CHECK: sub cl, bl, 123
11 sub cl, bl, 123
12 # CHECK: {nf} sub cl, bl, 123
14 {nf} sub cl, bl, 123
15 # CHECK: {evex} sub dx, 123
17 {evex} sub dx, 123
[all …]
/llvm-project/llvm/test/Transforms/InstCombine/
H A Dabs_abs.ll10 %sub = sub nsw i32 0, %x
11 %cond = select i1 %cmp, i32 %x, i32 %sub
13 %sub16 = sub nsw i32 0, %cond
24 %sub = sub nsw <2 x i32> zeroinitializer, %x
25 %cond = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %sub
27 %sub16 = sub nsw <2 x i32> zeroinitializer, %cond
38 %sub = sub nsw i32 0, %x
39 %cond = select i1 %cmp, i32 %x, i32 %sub
41 %sub16 = sub nsw i32 0, %cond
52 %sub = sub nsw i32 0, %x
[all …]
H A Dadd_or_sub.ll12 %sub = sub i32 0, %x
13 %or = or i32 %sub, %x
26 %sub = sub i8 0, %x
27 %or = or i8 %sub, %x
38 %sub = sub i128 0, %x
39 %or = or i128 %x, %sub
52 %sub
[all...]
H A Dsub-and-or-neg-xor.ll9 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
10 ; CHECK-NEXT: ret i32 [[SUB]]
14 %sub = sub i32 %and, %or
15 ret i32 %sub
21 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
22 ; CHECK-NEXT: call void @use(i32 [[SUB]])
23 ; CHECK-NEXT: ret i32 [[SUB]]
27 %sub = sub i32 %and, %or
28 call void @use(i32 %sub)
29 ret i32 %sub
[all …]
H A Dsub-xor-or-neg-and.ll9 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
10 ; CHECK-NEXT: ret i32 [[SUB]]
14 %sub = sub i32 %xor, %or
15 ret i32 %sub
21 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[TMP1]]
22 ; CHECK-NEXT: call void @use(i32 [[SUB]])
23 ; CHECK-NEXT: ret i32 [[SUB]]
27 %sub = sub i32 %xor, %or
28 call void @use(i32 %sub)
29 ret i32 %sub
[all …]
H A Dsub.ll11 %r = sub i32 %x, 42
19 ; CHECK-NEXT: [[R:%.*]] = sub i32 [[X:%.*]], ptrtoint (ptr @g to i32)
22 %r = sub i32 %x, ptrtoint (ptr @g to i32)
31 %r = sub <2 x i32> %x, <i32 42, i32 -12>
40 %r = sub <3 x i33> %x, <i33 -42, i33 42, i33 -12>
46 ; CHECK-NEXT: [[R:%.*]] = sub <4 x i32> [[X:%.*]], bitcast (i128 ptrtoint (ptr @g to i128) to <4 x i32>)
49 %r = sub <4 x i32> %x, bitcast (i128 ptrtoint (ptr @g to i128) to <4 x i32>)
58 %neg = sub i32 0, %x
59 %r = sub i32 %y, %neg
68 %neg = sub ns
[all...]
H A Dsub-or-and-xor.ll8 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
9 ; CHECK-NEXT: ret i32 [[SUB]]
13 %sub = sub i32 %or, %and
14 ret i32 %sub
19 ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
20 ; CHECK-NEXT: call void @use(i32 [[SUB]])
21 ; CHECK-NEXT: ret i32 [[SUB]]
25 %sub = sub i32 %or, %and
26 call void @use(i32 %sub)
27 ret i32 %sub
[all …]
H A Dunsigned_saturated_sub.ll11 ; usub_sat((sub nuw C1, A), C2) to usub_sat(usub_sat(C1 - C2), A)
17 %add = sub nuw i32 64, %a
26 %add = sub nuw i32 14, %a
35 %add = sub nuw i32 12, %a
46 %add = sub nuw <2 x i16> <i16 64, i16 64>, %a
56 %add = sub nuw <2 x i16> <i16 50, i16 64>, %a
65 %add = sub nuw <2 x i16> <i16 14, i16 14>, %a
74 %add = sub nuw <2 x i16> <i16 12, i16 12>, %a
83 %add = sub nuw <2 x i16> <i16 12, i16 13>, %a
91 ; CHECK-NEXT: [[ADD:%.*]] = sub i3
[all...]
H A Dicmp-sub.ll12 %y = sub nuw i64 10, %x
22 %y = sub nsw i64 3, %x
32 %y = sub nuw nsw i64 10, %x
42 %y = sub nuw nsw i64 10, %x
52 %y = sub nuw i64 10, %x
63 %y = sub nsw i64 10, %x
72 %y = sub nuw i64 10, %x
81 %y = sub nsw i8 127, %x
91 %s = sub i8 0, %y
101 %s = sub i
[all...]
H A Dzext-bool-add-sub.ll9 ; CHECK-NEXT: [[SUB:%.*]] = select i1 [[X:%.*]], i32 2, i32 1
10 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[SUB]], [[CONV3_NEG1]]
15 %conv3.neg = sub i32 0, %conv3
16 %sub = add i32 %conv, 1
17 %add = add i32 %sub, %conv3.neg
102 %sub = sub i64 0, %ext
103 ret i64 %sub
114 %sub = sub i6
[all...]
H A Dbit_ceil.ll9 ; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[CTLZ]]
16 %sub = sub i32 32, %ctlz
17 %shl = shl i32 1, %sub
28 ; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i64 0, [[CTLZ]]
35 %sub = sub i64 64, %ctlz
36 %shl = shl i64 1, %sub
46 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[X:%.*]], -2
47 ; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[SUB]], i
[all...]
H A Dsub-from-sub.ll12 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[X:%.*]], [[TMP1]]
15 %i0 = sub i8 %x, %y
16 %r = sub i8 %i0, %z
24 ; CHECK-NEXT: [[R:%.*]] = sub nuw nsw i8 [[X:%.*]], [[TMP1]]
27 %o0 = sub nuw nsw i8 %x, %y
28 %r = sub nuw nsw i8 %o0, %z
36 ; CHECK-NEXT: [[R:%.*]] = sub nuw i8 [[X:%.*]], [[TMP1]]
39 %o0 = sub nuw i8 %x, %y
40 %r = sub nuw i8 %o0, %z
48 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[X:%.*]], [[TMP1]]
[all …]
H A Dsub-ashr-and-to-icmp-select.ll5 ; E.g., clamp0 implemented in a shifty way, could be optimized as v > 0 ? v : 0, where sub hasNoSig…
19 %sub = sub nsw i8 %y, %x
20 %shr = ashr i8 %sub, 7
32 %sub = sub nsw i16 %y, %x
33 %shr = ashr i16 %sub, 15
44 %sub = sub nsw i32 %y, %x
45 %shr = ashr i32 %sub, 31
56 %sub = sub nsw i64 %y, %x
57 %shr = ashr i64 %sub, 63
70 %sub = sub nuw nsw i32 %y, %x
[all …]
/llvm-project/llvm/test/MC/AArch64/SME2/
H A Dsub.s15 sub za.s[w8, 0, vgx2], {z0.s, z1.s} // 11000001-10100000-00011100-00011000 label
16 // CHECK-INST: sub za.s[w8, 0, vgx2], { z0.s, z1.s }
21 sub za.s[w8, 0], {z0.s, z1.s} // 11000001-10100000-00011100-00011000 label
22 // CHECK-INST: sub za.s[w8, 0, vgx2], { z0.s, z1.s }
27 sub za.s[w10, 5, vgx2], {z10.s, z11.s} // 11000001-10100000-01011101-01011101 label
28 // CHECK-INST: sub za.s[w10, 5, vgx2], { z10.s, z11.s }
33 sub za.s[w10, 5], {z10.s, z11.s} // 11000001-10100000-01011101-01011101 label
34 // CHECK-INST: sub za.s[w10, 5, vgx2], { z10.s, z11.s }
39 sub za.s[w11, 7, vgx2], {z12.s, z13.s} // 11000001-10100000-01111101-10011111 label
40 // CHECK-INST: sub za.s[w11, 7, vgx2], { z12.s, z13.s }
[all …]
/llvm-project/llvm/test/MC/AArch64/SVE/
H A Dsub.s12 sub z0.h, z0.h, z0.h label
13 // CHECK-INST: sub z0.h, z0.h, z0.h
18 sub z21.b, z10.b, z21.b label
19 // CHECK-INST: sub z21.b, z10.b, z21.b
24 sub z31.d, p7/m, z31.d, z31.d label
25 // CHECK-INST: sub z31.d, p7/m, z31.d, z31.d
30 sub z23.h, p3/m, z23.h, z13.h label
31 // CHECK-INST: sub z23.h, p3/m, z23.h, z13.h
36 sub z31.h, z31.h, z31.h label
37 // CHECK-INST: sub z31.h, z31.h, z31.h
[all …]
/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
H A Dused-reduced-op.ll48 ; CHECK-NEXT: [[TMP33:%.*]] = sub <4 x i32> [[TMP32]], [[TMP0]]
50 ; CHECK-NEXT: [[TMP35:%.*]] = sub nsw <4 x i32> zeroinitializer, [[TMP33]]
55 ; CHECK-NEXT: [[SUB_116:%.*]] = sub i32 [[TMP30]], [[TMP1]]
57 ; CHECK-NEXT: [[NEG_117:%.*]] = sub nsw i32 0, [[SUB_116]]
61 ; CHECK-NEXT: [[SUB_1_1:%.*]] = sub i32 [[TMP30]], [[TMP2]]
63 ; CHECK-NEXT: [[NEG_1_1:%.*]] = sub nsw i32 0, [[SUB_1_1]]
68 ; CHECK-NEXT: [[SUB_2_1:%.*]] = sub i32 [[TMP30]], [[TMP3]]
70 ; CHECK-NEXT: [[NEG_2_1:%.*]] = sub nsw i32 0, [[SUB_2_1]]
75 ; CHECK-NEXT: [[SUB_3_1:%.*]] = sub i32 [[TMP30]], [[TMP4]]
77 ; CHECK-NEXT: [[NEG_3_1:%.*]] = sub nsw i32 0, [[SUB_3_1]]
[all …]
/llvm-project/llvm/test/CodeGen/LoongArch/ir-instruction/
H A Dsub.ll5 ;; Exercise the 'sub' LLVM IR: https://llvm.org/docs/LangRef.html#sub-instruction
10 ; LA32-NEXT: sub.w $a0, $a0, $a1
15 ; LA64-NEXT: sub.d $a0, $a0, $a1
17 %sub = sub i1 %x, %y
18 ret i1 %sub
24 ; LA32-NEXT: sub.w $a0, $a0, $a1
29 ; LA64-NEXT: sub.d $a0, $a0, $a1
31 %sub = sub i8 %x, %y
32 ret i8 %sub
38 ; LA32-NEXT: sub.w $a0, $a0, $a1
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dcombine-setcc.ll14 %sub = sext i1 %x to i32
16 %cmp = icmp eq i32 %sub, %conv3
28 %sub = sub nsw i32 0, %conv
30 %cmp = icmp eq i32 %sub, %conv1
43 %sub = sub nsw i32 0, %conv
45 %cmp = icmp eq i32 %sub, %conv1
58 %sub = sub nsw i32 0, %conv
60 %cmp = icmp eq i32 %sub, %conv1
72 %sub = sub nsw i32 0, %x
73 %cmp = icmp eq i32 %sub, %y
[all …]
/llvm-project/llvm/test/Transforms/SCCP/
H A Dsub-nuw-nsw-flags.ll8 ; CHECK-NEXT: [[SUB_1:%.*]] = sub nsw i8 [[A_SHR]], 1
9 ; CHECK-NEXT: [[SUB_2:%.*]] = sub i8 [[A_SHR]], -128
10 ; CHECK-NEXT: [[SUB_3:%.*]] = sub i8 [[A_SHR]], -127
11 ; CHECK-NEXT: [[SUB_4:%.*]] = sub i8 [[A_SHR]], -1
19 %sub.1 = sub i8 %a.shr, 1
20 %sub.2 = sub i8 %a.shr, 128
21 %sub.3 = sub i8 %a.shr, 129
22 %sub.4 = sub i8 %a.shr, -1
23 %res.1 = xor i8 %sub.1, %sub.2
24 %res.2 = xor i8 %res.1, %sub.3
[all …]
/llvm-project/llvm/test/MC/Hexagon/
H A Dalign.s5 { r1 = sub(#1, r1) }
6 # CHECK: 76414021 { r1 = sub(#1,r1)
12 { r1 = sub(#1, r1)
13 r2 = sub(#1, r2) }
14 # CHECK: 76414021 { r1 = sub(#1,r1)
15 # CHECK-NEXT: 76424022 r2 = sub(#1,r2)
20 { r1 = sub(#1, r1)
21 r2 = sub(#1, r2)
22 r3 = sub(#1, r3) }
23 # CHECK: 76434023 r3 = sub(#1,r3)
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dsink-addsub-of-const.ll30 ; add (sub %x, C), %y
37 ; CHECK-NEXT: sub w0, w8, #32
39 %t0 = sub i32 %a, 32
47 ; CHECK-NEXT: sub w0, w8, #32
49 %t0 = sub i32 %a, 32
54 ; add (sub C, %x), %y
60 ; CHECK-NEXT: sub w8, w1, w0
63 %t0 = sub i32 32, %a
70 ; CHECK-NEXT: sub w8, w1, w0
73 %t0 = sub i32 32, %a
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dint-sub-01.ll13 %sub = sub i32 %a, %b
14 ret i32 %sub
23 %sub = sub i32 %a, %b
24 ret i32 %sub
34 %sub = sub i32 %a, %b
35 ret i32 %sub
45 %sub = sub i32 %a, %b
46 ret i32 %sub
56 %sub = sub i32 %a, %b
57 ret i32 %sub
[all …]
H A Dint-sub-04.ll13 %sub = sub i64 %a, %b
14 ret i64 %sub
23 %sub = sub i64 %a, %b
24 ret i64 %sub
34 %sub = sub i64 %a, %b
35 ret i64 %sub
47 %sub = sub i64 %a, %b
48 ret i64 %sub
58 %sub = sub i64 %a, %b
59 ret i64 %sub
[all …]
/llvm-project/llvm/test/CodeGen/Lanai/
H A Dsub-cmp-peephole.ll9 ; CHECK-NEXT: sub %sp, 0x8, %sp
10 ; CHECK-NEXT: sub.f %r6, %r7, %r3
16 %sub = sub nsw i32 %a, %b
17 %sub. = select i1 %cmp, i32 %sub, i32 0
18 ret i32 %sub.
26 ; CHECK-NEXT: sub %sp, 0x8, %sp
27 ; CHECK-NEXT: sub.f %r7, %r6, %r3
33 %sub = sub nsw i32 %b, %a
34 %sub. = select i1 %cmp, i32 %sub, i32 0
35 ret i32 %sub.
[all …]

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