Lines Matching full:sub
11 %r = sub i32 %x, 42
19 ; CHECK-NEXT: [[R:%.*]] = sub i32 [[X:%.*]], ptrtoint (ptr @g to i32)
22 %r = sub i32 %x, ptrtoint (ptr @g to i32)
31 %r = sub <2 x i32> %x, <i32 42, i32 -12>
40 %r = sub <3 x i33> %x, <i33 -42, i33 42, i33 -12>
46 ; CHECK-NEXT: [[R:%.*]] = sub <4 x i32> [[X:%.*]], bitcast (i128 ptrtoint (ptr @g to i128) to <4 x i32>)
49 %r = sub <4 x i32> %x, bitcast (i128 ptrtoint (ptr @g to i128) to <4 x i32>)
58 %neg = sub i32 0, %x
59 %r = sub i32 %y, %neg
68 %neg = sub nsw i32 0, %x
69 %r = sub i32 %y, %neg
78 %neg = sub i32 0, %x
79 %r = sub nsw i32 %y, %neg
88 %neg = sub nsw i32 0, %x
89 %r = sub nsw i32 %y, %neg
98 %neg = sub <2 x i32> zeroinitializer, %x
99 %r = sub <2 x i32> %y, %neg
108 %neg = sub nsw <2 x i32> zeroinitializer, %x
109 %r = sub <2 x i32> %y, %neg
118 %neg = sub <2 x i32> zeroinitializer, %x
119 %r = sub nsw <2 x i32> %y, %neg
128 %neg = sub nsw <2 x i32> zeroinitializer, %x
129 %r = sub nsw <2 x i32> %y, %neg
138 %neg = sub <2 x i32> <i32 0, i32 poison>, %x
139 %r = sub <2 x i32> %y, %neg
148 %neg = sub nsw <2 x i32> <i32 poison, i32 0>, %x
149 %r = sub <2 x i32> %y, %neg
158 %neg = sub <2 x i32> <i32 poison, i32 0>, %x
159 %r = sub nsw <2 x i32> %y, %neg
170 %neg = sub nsw <2 x i32> <i32 0, i32 poison>, %x
171 %r = sub nsw <2 x i32> %y, %neg
184 ; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[Y]], [[X]]
187 ; CHECK-NEXT: ret i8 [[SUB]]
191 %sub = sub i8 %nx, %ny
194 ret i8 %sub
199 ; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i8> [[Y:%.*]], [[X:%.*]]
200 ; CHECK-NEXT: ret <2 x i8> [[SUB]]
204 %sub = sub <2 x i8> %nx, %ny
205 ret <2 x i8> %sub
210 ; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i8> [[Y:%.*]], [[X:%.*]]
211 ; CHECK-NEXT: ret <2 x i8> [[SUB]]
215 %sub = sub <2 x i8> %nx, %ny
216 ret <2 x i8> %sub
221 ; CHECK-NEXT: [[D_NEG:%.*]] = sub i32 [[C:%.*]], [[B:%.*]]
225 %D = sub i32 %B, %C
226 %E = sub i32 %A, %D
237 %D = sub i32 %A, %C
248 %D = sub i32 %A, %C
257 %B = sub i32 -1, %A
267 %C = sub i32 %B, %A
277 %C = sub i32 %A, %B
286 %C = sub i8 %A, %B
296 %C = sub <2 x i8> %A, %B
307 %C = sub i32 0, %B
317 %C = sub i32 0, %B
327 %C = sub <2 x i32> zeroinitializer, %B
337 %C = sub <2 x i32> zeroinitializer, %B
343 ; CHECK-NEXT: [[C:%.*]] = sub i32 0, [[A:%.*]]
347 %C = sub i32 0, %A
358 %Y = sub i32 0, %X
366 ; CHECK-NEXT: [[B:%.*]] = sub i32 0, [[A:%.*]]
370 %B = sub i32 0, %A
381 %i.8 = sub i64 %i.4, %i.12
390 %i.2 = sub i32 %g, %h
400 %i.2 = sub i32 %g, %h
411 %i2 = sub i32 0, %a
412 %i4 = sub i32 0, %b
423 %neg = sub i32 0, %shl
429 ; CHECK-NEXT: [[SUB_NEG:%.*]] = sub i64 [[B:%.*]], [[A:%.*]]
433 %sub = sub i64 %a, %b
434 %mul = shl i64 %sub, 2
435 %neg = sub i64 0, %mul
441 ; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[A:%.*]], [[B:%.*]]
442 ; CHECK-NEXT: store i64 [[SUB]], ptr [[P:%.*]], align 8
443 ; CHECK-NEXT: [[MUL_NEG:%.*]] = mul i64 [[SUB]], -4
446 %sub = sub i64 %a, %b
447 store i64 %sub, ptr %p
448 %mul = shl i64 %sub, 2
449 %neg = sub i64 0, %mul
455 ; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[A:%.*]], [[B:%.*]]
456 ; CHECK-NEXT: [[MUL:%.*]] = shl i64 [[SUB]], 2
458 ; CHECK-NEXT: [[NEG:%.*]] = sub i64 0, [[MUL]]
461 %sub = sub i64 %a, %b
462 %mul = shl i64 %sub, 2
464 %neg = sub i64 0, %mul
476 %neg = sub i64 0, %shl
488 %neg = sub i64 0, %shl
500 %neg = sub i64 0, %shl
512 %neg = sub i64 0, %ext
525 %neg = sub i64 0, %ext
532 ; CHECK-NEXT: [[SUB_NEG:%.*]] = sub i64 [[B:%.*]], [[A:%.*]]
537 %sub = sub i64 %a, %b
538 %shl = shl i64 %sub, 2
540 %neg = sub i32 0, %trunc
554 %neg = sub i32 0, %trunc
568 %neg = sub i32 0, %trunc
574 ; CHECK-NEXT: [[SUB_NEG:%.*]] = sub i64 [[B:%.*]], [[A:%.*]]
578 %sub = sub i64 %a, %b
579 %mul = mul i64 %sub, %c
580 %neg = sub i64 0, %mul
587 ; CHECK-NEXT: [[SUB_NEG:%.*]] = sub i64 [[B:%.*]], [[A:%.*]]
592 %sub = sub i64 %a, %b
593 %mul = mul i64 %complex, %sub
594 %neg = sub i64 0, %mul
601 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[MUL_NEG]], [[X:%.*]]
602 ; CHECK-NEXT: ret i32 [[SUB]]
605 %sub = sub i32 %x, %mul
606 ret i32 %sub
612 ; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]
613 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
616 %sub = sub <2 x i32> %x, %mul
617 ret <2 x i32> %sub
623 ; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]
624 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
627 %sub = sub <2 x i32> %x, %mul
628 ret <2 x i32> %sub
634 ; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]
635 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
638 %sub = sub <2 x i32> %x, %mul
639 ret <2 x i32> %sub
645 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[MUL_NEG]], [[X:%.*]]
646 ; CHECK-NEXT: ret i32 [[SUB]]
649 %sub = sub i32 %x, %mul
650 ret i32 %sub
656 ; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]
657 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
660 %sub = sub <2 x i32> %x, %mul
661 ret <2 x i32> %sub
667 ; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]
668 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
671 %sub = sub <2 x i32> %x, %mul
672 ret <2 x i32> %sub
678 ; CHECK-NEXT: [[SUB:%.*]] = add <2 x i32> [[MUL_NEG]], [[X:%.*]]
679 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
682 %sub = sub <2 x i32> %x, %mul
683 ret <2 x i32> %sub
689 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[X:%.*]], [[TMP1]]
690 ; CHECK-NEXT: ret i32 [[SUB]]
692 %neg = sub i32 0, %z
694 %sub = sub i32 %x, %mul
695 ret i32 %sub
701 ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[X:%.*]], [[TMP1]]
702 ; CHECK-NEXT: ret i32 [[SUB]]
704 %neg = sub i32 0, %z
706 %sub = sub i32 %x, %mul
707 ret i32 %sub
712 ; CHECK-NEXT: [[SUB:%.*]] = add <2 x i64> [[A:%.*]], <i64 3, i64 4>
713 ; CHECK-NEXT: ret <2 x i64> [[SUB]]
716 %sub = sub <2 x i64> <i64 2, i64 3>, %xor
717 ret <2 x i64> %sub
722 ; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i64> <i64 3, i64 4>, [[A:%.*]]
723 ; CHECK-NEXT: ret <2 x i64> [[SUB]]
726 %sub = sub <2 x i64> <i64 2, i64 3>, %add
727 ret <2 x i64> %sub
732 ; CHECK-NEXT: [[SUB:%.*]] = mul <2 x i64> [[A:%.*]], <i64 -2, i64 -3>
733 ; CHECK-NEXT: ret <2 x i64> [[SUB]]
736 %sub = sub <2 x i64> %A, %mul
737 ret <2 x i64> %sub
742 ; CHECK-NEXT: [[SUB:%.*]] = mul <2 x i64> [[A:%.*]], <i64 7, i64 15>
743 ; CHECK-NEXT: ret <2 x i64> [[SUB]]
746 %sub = sub <2 x i64> %shl, %A
747 ret <2 x i64> %sub
757 %sub = sub nsw <2 x i32> zeroinitializer, %div
758 ret <2 x i32> %sub
768 %sub = sub nsw i32 0, %div
769 ret i32 %sub
776 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 [[ASHR]], [[ASHR1]]
777 ; CHECK-NEXT: ret i16 [[SUB]]
781 %sub = sub i16 %ashr, %ashr1
782 ret i16 %sub
789 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[CONV]], [[CONV1]]
790 ; CHECK-NEXT: ret i32 [[SUB]]
794 %sub = sub i32 %conv, %conv1
795 ret i32 %sub
802 ; CHECK-NEXT: [[C:%.*]] = sub nsw i4 [[A]], [[B]]
807 %c = sub i4 %a, %b
815 ; CHECK-NEXT: [[C:%.*]] = sub nuw i4 [[A]], [[B]]
820 %c = sub i4 %a, %b
826 ; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[X:%.*]], -32768
827 ; CHECK-NEXT: ret i32 [[SUB]]
829 %sub = sub nsw i32 %x, 32768
830 ret i32 %sub
835 ; CHECK-NEXT: [[SUB:%.*]] = add nsw <2 x i32> [[X:%.*]], splat (i32 -32768)
836 ; CHECK-NEXT: ret <2 x i32> [[SUB]]
838 %sub = sub nsw <2 x i32> %x, <i32 32768, i32 32768>
839 ret <2 x i32> %sub
844 ; CHECK-NEXT: [[SUB:%.*]] = add nsw <vscale x 2 x i32> [[X:%.*]], splat (i32 -32768)
845 ; CHECK-NEXT: ret <vscale x 2 x i32> [[SUB]]
847 %sub = sub nsw <vscale x 2 x i32> %x, splat (i32 32768)
848 ret <vscale x 2 x i32> %sub
853 ; CHECK-NEXT: [[SUB:%.*]] = xor <2 x i16> [[X:%.*]], splat (i16 -32768)
854 ; CHECK-NEXT: ret <2 x i16> [[SUB]]
856 %sub = sub nsw <2 x i16> %x, <i16 -32768, i16 -32768>
857 ret <2 x i16> %sub
864 ; CHECK-NEXT: [[SUB:%.*]] = add <vscale x 2 x i16> [[X:%.*]], splat (i16 -32768)
865 ; CHECK-NEXT: ret <vscale x 2 x i16> [[SUB]]
867 %sub = sub nsw <vscale x 2 x i16> %x, splat (i16 -32768)
868 ret <vscale x 2 x i16> %sub
873 ; CHECK-NEXT: [[SUB:%.*]] = and i32 [[X:%.*]], [[Y:%.*]]
874 ; CHECK-NEXT: ret i32 [[SUB]]
878 %sub = sub i32 %or, %xor
879 ret i32 %sub
884 ; CHECK-NEXT: [[SUB:%.*]] = and i32 [[Y:%.*]], [[X:%.*]]
885 ; CHECK-NEXT: ret i32 [[SUB]]
889 %sub = sub i32 %or, %xor
890 ret i32 %sub
896 ; CHECK-NEXT: [[SUB:%.*]] = and i32 [[Y:%.*]], [[X_NOT]]
897 ; CHECK-NEXT: ret i32 [[SUB]]
900 %sub = sub i32 %or, %x
901 ret i32 %sub
907 ; CHECK-NEXT: [[SUB:%.*]] = and i32 [[Y:%.*]], [[X_NOT]]
908 ; CHECK-NEXT: ret i32 [[SUB]]
911 %sub = sub i32 %or, %x
912 ret i32 %sub
917 ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[D:%.*]], [[C:%.*]]
918 ; CHECK-NEXT: [[SUB:%.*]] = select i1 [[A:%.*]], i32 [[TMP1]], i32 0
919 ; CHECK-NEXT: ret i32 [[SUB]]
923 %sub = sub i32 %sel0, %sel1
924 ret i32 %sub
929 ; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[D:%.*]], [[C:%.*]]
930 ; CHECK-NEXT: [[SUB:%.*]] = select i1 [[A:%.*]], i32 0, i32 [[TMP1]]
931 ; CHECK-NEXT: ret i32 [[SUB]]
935 %sub = sub i32 %sel0, %sel1
936 ret i32 %sub
941 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 1, [[X:%.*]]
942 ; CHECK-NEXT: [[RES:%.*]] = and i32 [[SUB]], 64
945 %sub = sub i32 129, %X
946 %res = and i32 %sub, 64
952 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 1, [[X:%.*]]
953 ; CHECK-NEXT: [[RES:%.*]] = and i32 [[SUB]], 127
956 %sub = sub i32 129, %X
957 %res = and i32 %sub, 127
963 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 126, [[X:%.*]]
964 ; CHECK-NEXT: [[RES:%.*]] = and i32 [[SUB]], 64
967 %sub = sub i32 254, %X
968 %res = and i32 %sub, 64
974 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 126, [[X:%.*]]
975 ; CHECK-NEXT: [[RES:%.*]] = and i32 [[SUB]], 127
978 %sub = sub i32 254, %X
979 %res = and i32 %sub, 127
985 ; CHECK-NEXT: [[SUB:%.*]] = xor <2 x i1> [[B:%.*]], [[A:%.*]]
986 ; CHECK-NEXT: ret <2 x i1> [[SUB]]
988 %sub = sub <2 x i1> %A, %B
989 ret <2 x i1> %sub
998 %V = sub i32 123, %A
1008 %V = sub <2 x i32> <i32 123, i32 123>, %A
1018 %V = sub <2 x i32> <i32 123, i32 333>, %A
1040 %value = sub i32 123, %A
1062 %value = sub <2 x i32> <i32 123, i32 123>, %A
1084 %value = sub <2 x i32> <i32 123, i32 333>, %A
1090 ; CHECK-NEXT: [[Y:%.*]] = sub i32 0, [[B:%.*]]
1094 %Y = sub i32 %A, %X
1100 ; CHECK-NEXT: [[Y:%.*]] = sub i32 0, [[B:%.*]]
1104 %Y = sub i32 %A, %X
1113 ; CHECK-NEXT: [[GEPDIFF:%.*]] = sub i64 [[I:%.*]], [[J:%.*]]
1120 %sub = sub i64 %cast1, %cast2
1121 ret i64 %sub
1138 %sub = sub i64 %cast1, %cast2
1141 ret i64 %sub
1158 %sub = sub i64 %cast1, %cast2
1160 ret i64 %sub
1176 %sub = sub i64 %cast1, %cast2
1178 ret i64 %sub
1186 ; CHECK-NEXT: [[GEPDIFF:%.*]] = sub nsw i64 4200, [[GEP2_OFFS]]
1195 %sub = sub i64 %cast1, %cast2
1197 ret i64 %sub
1206 ; CHECK-NEXT: [[GEPDIFF:%.*]] = sub nsw i64 [[IDX1]], [[IDX2:%.*]]
1214 %sub = sub i64 %p1.int, %p2.int
1215 ret i64 %sub
1221 ; CHECK-NEXT: [[C:%.*]] = sub i32 2, [[TMP1]]
1224 %B = sub i32 1, %A
1232 ; CHECK-NEXT: [[C:%.*]] = sub <2 x i32> splat (i32 2), [[TMP1]]
1235 %B = sub <2 x i32> <i32 1, i32 1>, %A
1245 %B = sub i32 1, %A
1247 %D = sub i32 2, %C
1256 %B = sub <2 x i32> <i32 1, i32 1>, %A
1258 %D = sub <2 x i32> <i32 2, i32 2>, %C
1271 %res = sub i32 0, %3
1284 %res = sub i32 0, %3
1297 %res = sub i32 0, %3
1310 %res = sub i32 0, %3
1324 %res = sub <2 x i32> zeroinitializer, %3
1338 %res = sub <2 x i32> zeroinitializer, %3
1349 %C = sub i32 %B, 123
1357 ; CHECK-NEXT: [[D:%.*]] = sub i32 [[C]], [[B]]
1362 %D = sub i32 %C, %B
1375 %D = sub <2 x i32> %C, %B
1379 ; Check reversing sub operands won't trigger (X | Y) - Y --> X & ~Y
1383 ; CHECK-NEXT: [[D:%.*]] = sub i32 [[B]], [[C]]
1387 %D = sub i32 %B, %C
1395 ; CHECK-NEXT: [[Z:%.*]] = sub nuw nsw i32 [[X2]], [[Y2]]
1400 %z = sub i32 %x2, %y2
1408 ; CHECK-NEXT: [[Z:%.*]] = sub nsw i32 [[X2]], [[Y2]]
1413 %z = sub i32 %x2, %y2
1421 ; CHECK-NEXT: [[T1:%.*]] = sub i8 [[X]], [[T0]]
1426 %t1 = sub i8 %x, %t0
1439 %t1 = sub i8 %x, %t0
1449 ; CHECK-NEXT: [[S2:%.*]] = sub i8 [[TMP1]], [[TMP2]]
1452 %s1 = sub i8 %w, %x
1454 %s2 = sub i8 %a, %z
1465 ; CHECK-NEXT: [[S2:%.*]] = sub <2 x i8> [[TMP1]], [[TMP2]]
1469 %s1 = sub <2 x i8> %w, %x
1471 %s2 = sub <2 x i8> %a, %z
1482 ; CHECK-NEXT: [[S3:%.*]] = sub i8 [[TMP2]], [[TMP3]]
1485 %s1 = sub i8 %v, %w
1486 %s2 = sub i8 %x, %y
1488 %s3 = sub i8 %a, %z
1496 ; CHECK-NEXT: [[S1:%.*]] = sub i8 [[W:%.*]], [[X:%.*]]
1499 ; CHECK-NEXT: [[S2:%.*]] = sub i8 [[A]], [[Z:%.*]]
1502 %s1 = sub i8 %w, %x
1505 %s2 = sub i8 %a, %z
1513 ; CHECK-NEXT: [[S1:%.*]] = sub i8 [[W:%.*]], [[X:%.*]]
1516 ; CHECK-NEXT: [[S2:%.*]] = sub i8 [[A]], [[Z:%.*]]
1519 %s1 = sub i8 %w, %x
1522 %s2 = sub i8 %a, %z
1534 %r = sub i8 %a1, %a2
1544 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[A1]], [[A2]]
1549 %r = sub i8 %a1, %a2
1564 %r = sub <2 x i8> %a1, %a2
1570 ; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i16 [[X:%.*]], [[Y:%.*]]
1576 %r = sub nsw i16 %x8, %y8
1582 ; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[X:%.*]], [[Y:%.*]]
1588 %r = sub nuw i16 %x8, %y8
1594 ; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[X:%.*]], [[Y:%.*]]
1600 %r = sub i16 %x8, %y8
1606 ; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[X:%.*]], [[Y:%.*]]
1612 %r = sub nsw i16 %x8, %y8
1618 ; CHECK-NEXT: [[TMP1:%.*]] = sub nuw i16 [[X:%.*]], [[Y:%.*]]
1624 %r = sub nuw i16 %x8, %y8
1630 ; CHECK-NEXT: [[TMP1:%.*]] = sub i16 [[X:%.*]], [[Y:%.*]]
1636 %r = sub i16 %x8, %y8
1646 %r = sub i32 %a, %o
1657 %r = sub i32 %a, %o
1668 %r = sub i32 %a, %o
1680 %r = sub <2 x i8> %a, %o
1691 %r = sub i32 %a, %b
1702 %r = sub i32 %a, %b
1713 %r = sub i32 %a, %b
1724 %r = sub <2 x i8> %a, %b
1731 ; CHECK-NEXT: [[DOTNEG:%.*]] = sub i32 -11, [[TMP1]]
1734 %sub = sub i32 0, %a
1736 %sub1 = sub i32 %sub, %add
1743 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 [[X]], [[REM]]
1744 ; CHECK-NEXT: ret i8 [[SUB]]
1747 %sub = sub i8 %x, %rem
1748 ret i8 %sub
1754 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw <2 x i5> [[X]], [[REM]]
1755 ; CHECK-NEXT: ret <2 x i5> [[SUB]]
1758 %sub = sub <2 x i5> %x, %rem
1759 ret <2 x i5> %sub
1765 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw <3 x i32> <i32 255, i32 128, i32 0>, [[ZY]]
1769 %s = sub nuw <3 x i32> <i32 255, i32 128, i32 0>, %zy
1776 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw i32 257, [[ZY]]
1780 %s = sub nuw i32 257, %zy
1788 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw i32 [[ZX]], [[ZY]]
1793 %s = sub nuw i32 %zx, %zy
1801 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw <2 x i16> [[ZX]], [[SY]]
1806 %s = sub nuw <2 x i16> %zx, %sy
1814 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw i32 [[SX]], [[ZY]]
1819 %s = sub nuw i32 %sx, %zy
1828 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw i8 [[ZX]], [[ZY]]
1834 %s = sub nuw i8 %zx, %zy
1843 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw i8 [[ZX]], [[ZY]]
1849 %s = sub nuw i8 %zx, %zy
1859 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw i8 [[ZX]], [[ZY]]
1866 %s = sub nuw i8 %zx, %zy
1874 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw i32 [[ZX]], [[ZY]]
1879 %s = sub nuw i32 %zx, %zy
1888 %d = sub nsw i8 %x, %y
1891 %z = sub i16 %ex, %ed
1899 ; CHECK-NEXT: [[D:%.*]] = sub nsw i8 [[X:%.*]], [[Y:%.*]]
1902 ; CHECK-NEXT: [[Z:%.*]] = sub nsw i16 [[EX]], [[ED]]
1905 %d = sub nsw i8 %x, %y
1908 %z = sub i16 %ex, %ed
1916 ; CHECK-NEXT: [[D:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]]
1919 ; CHECK-NEXT: [[Z:%.*]] = sub nsw i16 [[EX]], [[ED]]
1922 %d = sub i8 %x, %y
1925 %z = sub i16 %ex, %ed
1933 ; CHECK-NEXT: [[D:%.*]] = sub nsw i8 [[X:%.*]], [[Y:%.*]]
1936 ; CHECK-NEXT: [[Z:%.*]] = sub nsw i16 [[EQ]], [[ED]]
1939 %d = sub nsw i8 %x, %y
1942 %z = sub i16 %eq, %ed
1955 %d = sub i8 %x, %r
1958 %z = sub i16 %sx, %sd
1967 %d = sub nuw i8 %x, %y
1970 %z = sub i16 %ex, %ed
1978 ; CHECK-NEXT: [[D:%.*]] = sub nuw i8 [[X:%.*]], [[Y:%.*]]
1981 ; CHECK-NEXT: [[Z:%.*]] = sub nsw i16 [[EX]], [[ED]]
1984 %d = sub nuw i8 %x, %y
1987 %z = sub i16 %ex, %ed
1995 ; CHECK-NEXT: [[D:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]]
1998 ; CHECK-NEXT: [[Z:%.*]] = sub nsw i16 [[EX]], [[ED]]
2001 %d = sub i8 %x, %y
2004 %z = sub i16 %ex, %ed
2012 ; CHECK-NEXT: [[D:%.*]] = sub nuw i8 [[X:%.*]], [[Y:%.*]]
2015 ; CHECK-NEXT: [[Z:%.*]] = sub nsw i16 [[EQ]], [[ED]]
2018 %d = sub nuw i8 %x, %y
2021 %z = sub i16 %eq, %ed
2034 %d = sub i8 %x, %r
2037 %z = sub i16 %ex, %ed
2051 %a = sub nsw i8 %m, %x
2064 %a = sub nuw <2 x i8> %m, %x
2072 ; CHECK-NEXT: [[M1:%.*]] = sub i8 1, [[Y:%.*]]
2077 %a = sub nsw i8 %x, %m
2083 ; CHECK-NEXT: [[M1:%.*]] = sub i8 1, [[Y:%.*]]
2088 %a = sub nuw i8 %x, %m
2098 ; CHECK-NEXT: [[A:%.*]] = sub i8 [[M]], [[X]]
2103 %a = sub i8 %m, %x
2110 ; CHECK-NEXT: [[A:%.*]] = sub i8 [[Y:%.*]], [[M]]
2116 %a = sub i8 %y, %m
2127 ; CHECK-NEXT: [[A:%.*]] = sub i8 [[Y:%.*]], [[M]]
2133 %a = sub i8 %y, %m
2144 ; CHECK-NEXT: [[A:%.*]] = sub i8 [[M]], [[Y:%.*]]
2146 ; CHECK-NEXT: [[S:%.*]] = sub i8 [[A]], [[Z:%.*]]
2151 %a = sub i8 %m, %y
2153 %s = sub i8 %a, %z
2158 ; sub becomes negate and combines with shl
2166 %sub = sub i8 7, %x000
2167 %r = and i8 %sub, -8 ; 3 low bits are not demanded
2176 ; CHECK-NEXT: [[SUB:%.*]] = sub i8 7, [[X000]]
2177 ; CHECK-NEXT: call void @use8(i8 [[SUB]])
2178 ; CHECK-NEXT: [[R:%.*]] = and i8 [[SUB]], -8
2182 %sub = sub i8 7, %x000
2183 call void @use8(i8 %sub)
2184 %r = and i8 %sub, -8 ; 3 low bits are not demanded
2193 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 24, [[X000]]
2194 ; CHECK-NEXT: [[R:%.*]] = and i8 [[SUB]], -16
2198 %sub = sub nsw i8 30, %x000 ; 0b0001_1110
2199 %r = and i8 %sub, -16 ; 4 low bits are not demanded
2208 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw <2 x i8> splat (i8 24), [[X0000]]
2209 ; CHECK-NEXT: [[R:%.*]] = lshr exact <2 x i8> [[SUB]], splat (i8 3)
2213 %sub = sub nuw <2 x i8> <i8 31, i8 31>, %x0000
2214 %r = lshr <2 x i8> %sub, <i8 3, i8 3> ; 3 low bits are not demanded
2223 ; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[Y:%.*]], [[X000]]
2224 ; CHECK-NEXT: [[R:%.*]] = and i8 [[SUB]], -8
2229 %sub = sub i8 %y000, %x000
2230 %r = and i8 %sub, -8 ; 3 low bits are not demanded
2239 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i8 [[Y:%.*]], [[X0000]]
2240 ; CHECK-NEXT: [[R:%.*]] = lshr i8 [[SUB]], 4
2245 %sub = sub nsw nuw i8 %y111, %x0000
2246 %r = lshr i8 %sub, 4 ; 4 low bits are not demanded
2256 ; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[Y00000]], [[X0000]]
2257 ; CHECK-NEXT: [[R:%.*]] = lshr exact i8 [[SUB]], 4
2262 %sub = sub i8 %y00000, %x0000
2263 %r = lshr i8 %sub, 4 ; 4 low bits are not demanded
2277 %sub = sub nuw i10 71, %x
2278 %and = and i10 %sub, 120
2279 %r = sub i10 443, %and
2292 %sub = sub i10 71, %x
2293 %and = and i10 %sub, -8
2294 %r = sub i10 33, %and
2302 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw i10 71, [[X:%.*]]
2303 ; CHECK-NEXT: [[AND:%.*]] = and i10 [[SUB]], 120
2307 %sub = sub nuw i10 71, %x
2308 %and = and i10 %sub, 120
2316 ; CHECK-NEXT: [[SUB:%.*]] = sub i10 71, [[X:%.*]]
2317 ; CHECK-NEXT: [[AND:%.*]] = and i10 [[SUB]], 248
2318 ; CHECK-NEXT: [[R:%.*]] = sub nuw nsw i10 444, [[AND]]
2321 %sub = sub nuw i10 327, %x
2322 %and = and i10 %sub, 248
2323 %r = sub i10 444, %and
2330 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw i10 71, [[X:%.*]]
2331 ; CHECK-NEXT: [[AND:%.*]] = and i10 [[SUB]], 88
2332 ; CHECK-NEXT: [[R:%.*]] = sub nsw i10 64, [[AND]]
2335 %sub = sub nuw i10 71, %x
2336 %and = and i10 %sub, 88
2337 %r = sub i10 64, %and
2344 ; CHECK-NEXT: [[SUB:%.*]] = sub i10 71, [[X:%.*]]
2345 ; CHECK-NEXT: [[AND:%.*]] = and i10 [[SUB]], 120
2346 ; CHECK-NEXT: [[R:%.*]] = sub nsw i10 64, [[AND]]
2349 %sub = sub i10 71, %x
2350 %and = and i10 %sub, 120
2351 %r = sub i10 64, %and
2360 ; CHECK-NEXT: [[SUB:%.*]] = sub i10 71, [[X:%.*]]
2361 ; CHECK-NEXT: [[AND:%.*]] = and i10 [[SUB]], 120
2362 ; CHECK-NEXT: [[R:%.*]] = sub nsw i10 64, [[AND]]
2366 %sub = sub i10 71, %x
2367 %and = and i10 %sub, 120
2368 %r = sub i10 64, %and
2380 %sub = sub nuw <2 x i8> <i8 71, i8 71>, %x
2381 %and = and <2 x i8> %sub, <i8 120, i8 120>
2382 %r = sub <2 x i8> <i8 55, i8 55>, %and
2389 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw <2 x i8> <i8 71, i8 poison>, [[X:%.*]]
2390 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[SUB]], splat (i8 120)
2391 ; CHECK-NEXT: [[R:%.*]] = sub nsw <2 x i8> splat (i8 77), [[AND]]
2394 %sub = sub nuw <2 x i8> <i8 71, i8 poison>, %x
2395 %and = and <2 x i8> %sub, <i8 120, i8 120>
2396 %r = sub <2 x i8> <i8 77, i8 77>, %and
2403 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw <2 x i8> splat (i8 71), [[X:%.*]]
2404 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[SUB]], <i8 120, i8 poison>
2405 ; CHECK-NEXT: [[R:%.*]] = sub nsw <2 x i8> splat (i8 44), [[AND]]
2408 %sub = sub nuw <2 x i8> <i8 71, i8 71>, %x
2409 %and = and <2 x i8> %sub, <i8 120, i8 poison>
2410 %r = sub <2 x i8> <i8 44, i8 44>, %and
2417 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw <2 x i8> splat (i8 71), [[X:%.*]]
2418 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i8> [[SUB]], splat (i8 120)
2419 ; CHECK-NEXT: [[R:%.*]] = sub nsw <2 x i8> <i8 88, i8 poison>, [[AND]]
2422 %sub = sub nuw <2 x i8> <i8 71, i8 71>, %x
2423 %and = and <2 x i8> %sub, <i8 120, i8 120>
2424 %r = sub <2 x i8> <i8 88, i8 poison>, %and
2433 ; CHECK-NEXT: [[SUB:%.*]] = sub i8 [[X]], [[Y]]
2434 ; CHECK-NEXT: [[R:%.*]] = mul i8 [[ADD]], [[SUB]]
2439 %r = sub i8 %x2, %y2
2448 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw i5 [[X]], [[Y]]
2449 ; CHECK-NEXT: [[R:%.*]] = mul nuw i5 [[ADD]], [[SUB]]
2454 %r = sub nuw i5 %x2, %y2
2463 ; CHECK-NEXT: [[SUB:%.*]] = sub i5 [[X]], [[Y]]
2464 ; CHECK-NEXT: [[R:%.*]] = mul i5 [[ADD]], [[SUB]]
2469 %r = sub i5 %x2, %y2
2478 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw <2 x i5> [[X]], [[Y]]
2479 ; CHECK-NEXT: [[R:%.*]] = mul nsw <2 x i5> [[ADD]], [[SUB]]
2484 %r = sub nsw <2 x i5> %x2, %y2
2493 ; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i5> [[X]], [[Y]]
2494 ; CHECK-NEXT: [[R:%.*]] = mul <2 x i5> [[ADD]], [[SUB]]
2499 %r = sub nsw <2 x i5> %x2, %y2
2509 %r = sub nsw i1 %x2, %y2
2520 %r = sub nuw i1 %x2, %y2
2530 ; CHECK-NEXT: [[SUB:%.*]] = sub i2 [[X]], [[Y]]
2531 ; CHECK-NEXT: [[R:%.*]] = mul i2 [[ADD]], [[SUB]]
2536 %r = sub nsw i2 %x2, %y2
2545 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw i2 [[X]], [[Y]]
2546 ; CHECK-NEXT: [[R:%.*]] = mul nuw i2 [[ADD]], [[SUB]]
2551 %r = sub nuw i2 %x2, %y2
2562 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[X2]], [[Y2]]
2568 %r = sub i8 %x2, %y2
2579 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[X2]], [[Y2]]
2585 %r = sub i8 %x2, %y2
2595 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[M]], [[Y2]]
2600 %r = sub i8 %m, %y2
2610 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[X2]], [[M]]
2615 %r = sub i8 %x2, %m
2623 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[X]], [[Y]]
2630 %r = sub i8 %xz, %yz
2640 ; CHECK-NEXT: [[R:%.*]] = sub i8 [[XC]], [[YC]]
2647 %r = sub i8 %xc, %yc
2655 ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 [[X:%.*]], [[Y:%.*]]
2661 %r = sub i8 %xc, %yc
2670 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 [[X]], [[Y]]
2671 ; CHECK-NEXT: ret i32 [[SUB]]
2679 %sub = sub i32 %x, %y
2680 ret i32 %sub
2701 %sub = sub i32 %x, %y
2702 %ext2 = zext i32 %sub to i64
2716 ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[X]], [[Y]]
2717 ; CHECK-NEXT: [[EXT:%.*]] = zext nneg i32 [[SUB]] to i64
2726 %sub = sub i32 %x, %y
2727 %ext = zext i32 %sub to i64
2749 %sub = sub nsw i32 %y, %x
2750 %cmp = icmp eq i32 %sub, -1
2764 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[X]], [[Y]]
2765 ; CHECK-NEXT: ret i32 [[SUB]]
2773 %sub = sub i32 %x, %y
2774 ret i32 %sub
2785 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[X]], [[Y]]
2786 ; CHECK-NEXT: ret i32 [[SUB]]
2794 %sub = sub i32 %x, %y
2795 ret i32 %sub
2809 %sub = sub i32 63, %x
2810 %and = and i32 %sub, 63
2822 %sub = sub i32 63, %x
2823 %and = and i32 %sub, 63
2836 %sub = sub i32 63, %x
2837 %and = and i32 %sub, 31
2846 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[X:%.*]]
2847 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], 63
2851 %sub = sub i32 %y, %x
2852 %and = and i32 %sub, 63
2859 ; CHECK-NEXT: [[SUB:%.*]] = sub i32 63, [[X:%.*]]
2860 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], 127
2864 %sub = sub i32 63, %x
2865 %and = and i32 %sub, 127