Searched +full:socfpga +full:- +full:lwhps2fpga +full:- +full:bridge (Results 1 – 5 of 5) sorted by relevance
| /freebsd-src/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | altera-hps2fpga-bridge.txt | 1 Altera FPGA/HPS Bridge Driver
4 - regs : base address and size for AXI bridge module
5 - compatible : Should contain one of:
6 "altr,socfpga-lwhps2fpga-bridge",
7 "altr,socfpga-hps2fpga-bridge", or
8 "altr,socfpga-fpga2hps-bridge"
9 - resets : Phandle and reset specifier for this bridge's reset
10 - clocks : Clocks used by this module.
12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
15 fpga_bridge0: fpga-bridge@ff400000 {
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| H A D | altr,socfpga-hps2fpga-bridge.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera FPGA/HPS Bridge
10 - Xu Yilun <yilun.xu@intel.com>
13 - $ref: fpga-bridge.yaml#
18 - altr,socfpga-lwhps2fpga-bridge
19 - altr,socfpga-hps2fpga-bridge
20 - altr,socfpga-fpga2hps-bridge
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| H A D | fpga-region.txt | 6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
57 FPGA Bridge
64 * During Partial Reconfiguration of a specific region, that region's bridge
70 own bridge and its own split of the busses in the FPGA.
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| /freebsd-src/sys/arm/altera/socfpga/ |
| H A D | socfpga_rstmgr.c | |
| /freebsd-src/sys/contrib/device-tree/src/arm/intel/socfpga/ |
| H A D | socfpga.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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