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/llvm-project/clang/include/clang/Basic/
H A Darm_fp16.td20 def VNEGSH : SInst<"vneg", "11", "Sh">;
23 def SCALAR_FRECPSH : IInst<"vrecps", "111", "Sh">;
24 def FSQRTSH : SInst<"vsqrt", "11", "Sh">;
25 def SCALAR_FRSQRTSH : IInst<"vrsqrts", "111", "Sh">;
28 def SCALAR_FRECPEH : IInst<"vrecpe", "11", "Sh">;
31 def SCALAR_FRECPXH : IInst<"vrecpx", "11", "Sh">;
34 def SCALAR_FRSQRTEH : IInst<"vrsqrte", "11", "Sh">;
37 def FRINTZ_S64H : SInst<"vrnd", "11", "Sh">;
38 def FRINTA_S64H : SInst<"vrnda", "11", "Sh">;
39 def FRINTI_S64H : SInst<"vrndi", "11", "Sh">;
[all...]
/llvm-project/llvm/test/Analysis/ValueTracking/
H A Dnumsignbits-from-assume.ll9 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[ADD]], 3
10 ; CHECK-NEXT: ret i32 [[SH]]
15 %sh = shl i32 %add, 3
16 ret i32 %sh
24 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[ADD]], 3
25 ; CHECK-NEXT: ret i32 [[SH]]
30 %sh = shl i32 %add, 3
31 ret i32 %sh
39 ; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
40 ; CHECK-NEXT: ret i32 [[SH]]
[all...]
/llvm-project/llvm/test/Transforms/InstCombine/
H A Dicmp-topbitssame.ll14 %sh = lshr i16 %add, 8
15 %conv.i = trunc i16 %sh to i8
28 %sh = lshr i16 %add, 8
29 %conv.i = trunc i16 %sh to i8
42 %sh = lshr i16 %add, 8
43 %conv.i = trunc i16 %sh to i8
56 %sh = lshr i16 %add, 8
57 %conv.i = trunc i16 %sh to i8
70 %sh = lshr i64 %add, 32
71 %conv.i = trunc i64 %sh to i32
[all …]
H A Dxor-ashr.ll16 %sh = ashr i8 %add, 7
17 %x = xor i8 %sh, 127
27 %sh = ashr i16 %add, 15
28 %t = trunc i16 %sh to i8
39 %sh = ashr i64 %add, 63
40 %t = trunc i64 %sh to i32
51 %sh = ashr i128 %add, 127
52 %x = xor i128 %sh, 27
62 %sh = ashr <4 x i16> %add, <i16 15, i16 15, i16 15, i16 15>
63 %t = trunc <4 x i16> %sh t
[all...]
H A Dbitwiselogic-bitmanip.ll4 define i32 @test_or_fshl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) {
6 ; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) {
9 ; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[SH]])
12 %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh)
13 %val2 = call i32 @llvm.fshl.i32(i32 %c, i32 %d, i32 %sh)
17 define i32 @test_and_fshl(i32 %a, i32 %b, i32 %c, i32 %d, i32 %sh) {
19 ; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]], i32 [[SH:%.*]]) {
22 ; CHECK-NEXT: [[RET:%.*]] = call i32 @llvm.fshl.i32(i32 [[TMP1]], i32 [[TMP2]], i32 [[SH]])
25 %val1 = call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %sh)
26 %val2 = call i32 @llvm.fshl.i32(i32 %c, i32 %d, i32 %sh)
[all …]
H A Dadd-shift.ll3 define i8 @flip_add_of_shift_neg(i8 %v, i8 %sh, i8 %x) {
5 ; CHECK-SAME: (i8 [[V:%.*]], i8 [[SH:%.*]], i8 [[X:%.*]]) {
6 ; CHECK-NEXT: [[TMP1:%.*]] = shl i8 [[V]], [[SH]]
11 %sv = shl nuw nsw i8 %nv, %sh
16 define <2 x i8> @flip_add_of_shift_neg_vec(<2 x i8> %v, <2 x i8> %sh, <2 x i8> %xx) {
18 ; CHECK-SAME: (<2 x i8> [[V:%.*]], <2 x i8> [[SH:%.*]], <2 x i8> [[XX:%.*]]) {
20 ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i8> [[V]], [[SH]]
26 %sv = shl <2 x i8> %nv, %sh
31 define i8 @flip_add_of_shift_neg_fail_shr(i8 %v, i8 %sh, i8 %x) {
33 ; CHECK-SAME: (i8 [[V:%.*]], i8 [[SH:%.*]], i8 [[X:%.*]]) {
[all …]
H A Dand2.ll138 %sh = shl i8 1, %x
139 %and = and i8 %sh, 1
147 ; CHECK-NEXT: [[SH:%.*]] = shl nuw i8 1, [[X:%.*]]
148 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[SH]], 1
149 ; CHECK-NEXT: [[ADD:%.*]] = add nuw i8 [[SH]], [[AND]]
152 %sh = shl i8 1, %x
153 %and = and i8 %sh, 1
154 %add = add i8 %sh, %and
166 %sh = shl <2 x i8> <i8 1, i8 1>, %x
167 %and = and <2 x i8> %sh, <i
[all...]
H A Dlshr.ll22 ; CHECK-NEXT: [[SH:%.*]] = zext i1 [[TMP1]] to i32
23 ; CHECK-NEXT: ret i32 [[SH]]
26 %sh = lshr i32 %ct, 5
27 ret i32 %sh
33 ; CHECK-NEXT: [[SH:%.*]] = zext i1 [[TMP1]] to i32
34 ; CHECK-NEXT: ret i32 [[SH]]
37 %sh = lshr i32 %ct, 5
38 ret i32 %sh
44 ; CHECK-NEXT: [[SH:%.*]] = zext i1 [[TMP1]] to i32
45 ; CHECK-NEXT: ret i32 [[SH]]
[all...]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dshift-12.ll8 define i32 @f1(i32 %a, i32 %sh) {
14 %and = and i32 %sh, 31
20 define i32 @f2(i32 %a, i32 %sh) {
25 %and = and i32 %sh, 63
31 define i32 @f3(i32 %a, i32 %sh) {
36 %and = and i32 %sh, 255
42 define i32 @f4(i32 %a, i32 %sh) {
47 %and = and i32 %sh, 63
53 define i32 @f5(i32 %a, i32 %sh) {
58 %and = and i32 %sh, 63
[all …]
H A Drot-shift-64-sub-amt.ll7 define i64 @f1(i64 %in, i64 %sh) {
13 %sub = sub i64 64, %sh
18 define i64 @f2(i64 %in, i64 %sh) {
24 %sub = sub i64 64, %sh
29 define i64 @f3(i64 %in, i64 %sh) {
35 %sub = sub i64 64, %sh
40 define i64 @f4(i64 %in, i64 %sh) {
46 %shr = lshr i64 %in, %sh
47 %sub = sub i64 64, %sh
53 define i64 @f5(i64 %in, i64 %sh) {
[all …]
H A Dshift-11.ll7 define i32 @f1(i32 %a, i32 %sh) {
13 %and = and i32 %sh, 31
19 define i32 @f2(i32 %a, i32 %sh) {
25 %and = and i32 %sh, 31
31 define i32 @f3(i32 %a, i32 %sh) {
37 %and = and i32 %sh, 31
43 define i64 @f4(i64 %a, i64 %sh) {
49 %and = and i64 %sh, 31
55 define i64 @f5(i64 %a, i64 %sh) {
61 %and = and i64 %sh, 31
[all …]
/llvm-project/clang-tools-extra/clangd/test/
H A Dsystem-include-extractor.test11 # RUN: echo '#!/bin/sh' >> %t.dir/bin/my_driver.sh
12 # RUN: echo '[ "$0" = "%t.dir/bin/my_driver.sh" ] || exit' >> %t.dir/bin/my_driver.sh
13 …'[ "$1" = "-print-file-name=include" ] && echo "%t.dir/builtin" && exit' >> %t.dir/bin/my_driver.sh
14 # RUN: echo 'args="$*"' >> %t.dir/bin/my_driver.sh
17 # RUN: echo '[ -z "${args##*"-nostdinc"*}" ] || exit' >> %t.dir/bin/my_driver.sh
18 # RUN: echo '[ -z "${args##*"--sysroot /my/sysroot/path"*}" ] || exit' >> %t.dir/bin/my_driver.sh
19 # RUN: echo '[ -z "${args##*"-isysroot /isysroot"*}" ] || exit' >> %t.dir/bin/my_driver.sh
20 # RUN: echo '[ -z "${args##*"-target arm-linux-gnueabihf"*}" ] || exit' >> %t.dir/bin/my_driver.sh
21 # RUN: echo '[ -z "${args##*"--stdlib libc++"*}" ] || exit' >> %t.dir/bin/my_driver.sh
22 # RUN: echo '[ -z "${args##*"-specs=test.spec"*}" ] || exit' >> %t.dir/bin/my_driver.sh
[all …]
/llvm-project/lldb/docs/use/
H A Dqemu-testing.rst
/llvm-project/llvm/test/CodeGen/X86/
H A Dlea-dagdag.ll16 %sh = shl i16 %t5, 2
17 %t6 = add i16 %sh, %t0
31 %sh = shl i8 %t4, 2
32 %t5 = zext i8 %sh to i16
47 %sh = shl i32 %t5, 3
48 %t6 = add i32 %sh, %t0
61 %sh = shl i8 %t4, 3
62 %t5 = zext i8 %sh to i32
77 %sh = shl i32 %t5, 2
78 %t6 = add i32 %sh, %t0
[all …]
H A Dshift-double-x86_64.ll18 %sh = or i64 %sh_lo, %sh_hi
19 ret i64 %sh
34 %sh = or i64 %sh_lo, %sh_hi
35 ret i64 %sh
49 %sh = or i64 %sh_lo, %sh_hi
50 ret i64 %sh
64 %sh = or i64 %sh_lo, %sh_hi
65 ret i64 %sh
80 %sh = or i64 %sh_lo, %sh_hi
81 ret i64 %sh
[all …]
H A Dnegate-shift.ll10 %sh = lshr i32 %x, 31
11 %neg = sub i32 0, %sh
21 %sh = ashr i64 %x, 63
22 %neg = sub i64 0, %sh
31 %sh = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
32 %neg = sub <4 x i32> zeroinitializer, %sh
41 %sh = lshr <8 x i16> %x, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
42 %neg = sub <8 x i16> zeroinitializer, %sh
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dsve2-rsh.ll13 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)
14 ret <vscale x 2 x i64> %sh
26 %sh = lshr <vscale x 2 x i64> %add, %y
27 ret <vscale x 2 x i64> %sh
38 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)
39 ret <vscale x 2 x i64> %sh
53 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)
55 ret <vscale x 2 x i64> %sh
66 %sh = lshr <vscale x 2 x i64> %add, splat (i64 6)
67 ret <vscale x 2 x i64> %sh
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A Durem-vector-lkk.ll42 ; RV32I-NEXT: sh s4, 0(s3)
43 ; RV32I-NEXT: sh s0, 2(s3)
44 ; RV32I-NEXT: sh s1, 4(s3)
45 ; RV32I-NEXT: sh a0, 6(s3)
86 ; RV32IM-NEXT: sh a2, 0(a0)
87 ; RV32IM-NEXT: sh a3, 2(a0)
88 ; RV32IM-NEXT: sh a4, 4(a0)
89 ; RV32IM-NEXT: sh a1, 6(a0)
121 ; RV64I-NEXT: sh s4, 0(s3)
122 ; RV64I-NEXT: sh s
[all...]
H A Dsrem-vector-lkk.ll41 ; RV32I-NEXT: sh s4, 0(s3)
42 ; RV32I-NEXT: sh s0, 2(s3)
43 ; RV32I-NEXT: sh s1, 4(s3)
44 ; RV32I-NEXT: sh a0, 6(s3)
98 ; RV32IM-NEXT: sh a3, 0(a0)
99 ; RV32IM-NEXT: sh a2, 2(a0)
100 ; RV32IM-NEXT: sh a4, 4(a0)
101 ; RV32IM-NEXT: sh a1, 6(a0)
133 ; RV64I-NEXT: sh s4, 0(s3)
134 ; RV64I-NEXT: sh s
[all...]
/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dtstbit.ll34 %sh = lshr i64 %x, 37
35 %m = and i64 %sh, 1
51 %sh = lshr i64 %x, 27
52 %m = and i64 %sh, 1
67 %sh = lshr i32 %x, 27
68 %n = xor i32 %sh, -1
83 %sh = lshr i16 %x, 7
84 %m = and i16 %sh, 1
99 %sh = lshr i8 %x, 3
100 %m = and i8 %sh, 1
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dthumb2-shifter.ll41 define i32 @t2ADDrs_noRegShift(i32 %X, i32 %Y, i8 %sh) {
50 %shift.upgrd.1 = zext i8 %sh to i32
56 define i32 @t2ADDrs_noRegShift2(i32 %X, i32 %Y, i8 %sh) {
65 %shift.upgrd.1 = zext i8 %sh to i32
71 define i32 @t2ADDrs_noRegShift3(i32 %X, i32 %Y, i8 %sh) {
80 %shift.upgrd.1 = zext i8 %sh to i32
86 define i32 @t2ADDrs_optsize(i32 %X, i32 %Y, i8 %sh) optsize {
90 %shift.upgrd.1 = zext i8 %sh to i32
96 define i32 @t2ADDrs_minsize(i32 %X, i32 %Y, i8 %sh) minsize {
100 %shift.upgrd.1 = zext i8 %sh to i32
H A Dmve-pred-shuffle.ll25 %sh = shufflevector <2 x i1> %c, <2 x i1> undef, <2 x i32> <i32 1, i32 0>
26 %s = select <2 x i1> %sh, <2 x i64> %a, <2 x i64> %b
50 %sh = shufflevector <4 x i1> %c, <4 x i1> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
51 %s = select <4 x i1> %sh, <4 x i32> %a, <4 x i32> %b
75 …%sh = shufflevector <8 x i1> %c, <8 x i1> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32…
76 %s = select <8 x i1> %sh, <8 x i16> %a, <8 x i16> %b
100 …%sh = shufflevector <16 x i1> %c, <16 x i1> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32…
101 %s = select <16 x i1> %sh, <16 x i8> %a, <16 x i8> %b
126 %sh = shufflevector <2 x i1> %c, <2 x i1> undef, <2 x i32> <i32 0, i32 1>
127 %s = select <2 x i1> %sh, <2 x i64> %a, <2 x i64> %b
[all …]
/llvm-project/llvm/test/CodeGen/Lanai/
H A Dconstant_multiply.ll15 ; CHECK-NEXT: sh %r6, 0x1, %r3
16 ; CHECK-NEXT: sh %r6, 0x3, %r9
31 ; CHECK-NEXT: sh %r6, 0x3, %r3
46 ; CHECK-NEXT: sh %r6, 0x3, %rv
60 ; CHECK-NEXT: sh %r6, 0x3, %r3
75 ; CHECK-NEXT: sh %r6, 0x1, %r3
76 ; CHECK-NEXT: sh %r6, 0x3, %r9
91 ; CHECK-NEXT: sh %r6, 0x8, %r3
92 ; CHECK-NEXT: sh %r6, 0xa, %r9
107 ; CHECK-NEXT: sh %r6, 0x3, %r3
[all …]
/llvm-project/libcxx/utils/ci/
H A DDockerfile136 wget https://apt.llvm.org/llvm.sh -O /tmp/llvm.sh
137 chmod +x /tmp/llvm.sh
138 sudo /tmp/llvm.sh $(($LLVM_HEAD_VERSION - 3)) all # for CI transitions
139 sudo /tmp/llvm.sh $(($LLVM_HEAD_VERSION - 2)) all # previous release
140 sudo /tmp/llvm.sh $(($LLVM_HEAD_VERSION - 1)) all # latest release
141 sudo /tmp/llvm.sh $LLVM_HEAD_VERSION all # current ToT
163 wget https://github.com/Kitware/CMake/releases/download/v3.24.4/cmake-3.24.4-linux-x86_64.sh -O /tmp/install-cmake.sh
164 sudo bash /tmp/install-cmake.sh
[all...]
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dmerge-stores-truncating.ll10 %sh = lshr i16 %x, 8
11 %t2 = trunc i16 %sh to i8
46 %sh = lshr i32 %x, 16
47 %t2 = trunc i32 %sh to i16
150 %sh = lshr i64 %x, 32
151 %t2 = trunc i64 %sh to i32
199 %sh = lshr i32 %x, 16
200 %x01 = trunc i32 %sh to i16
213 %sh = lshr i32 %x, 16
214 %x01 = trunc i32 %sh to i16
[all …]

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