xref: /llvm-project/llvm/test/CodeGen/SystemZ/shift-12.ll (revision a65ccc1b9fe740c9f65d9cf2b627de50278aad56) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test removal of AND operations that don't affect last 6 bits of shift amount
3; operand.
4;
5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
6
7; Test that AND is not removed when some lower 6 bits are not set.
8define i32 @f1(i32 %a, i32 %sh) {
9; CHECK-LABEL: f1:
10; CHECK:       # %bb.0:
11; CHECK-NEXT:    nill %r3, 31
12; CHECK-NEXT:    sll %r2, 0(%r3)
13; CHECK-NEXT:    br %r14
14  %and = and i32 %sh, 31
15  %shift = shl i32 %a, %and
16  ret i32 %shift
17}
18
19; Test removal of AND mask with only bottom 6 bits set.
20define i32 @f2(i32 %a, i32 %sh) {
21; CHECK-LABEL: f2:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    sll %r2, 0(%r3)
24; CHECK-NEXT:    br %r14
25  %and = and i32 %sh, 63
26  %shift = shl i32 %a, %and
27  ret i32 %shift
28}
29
30; Test removal of AND mask including but not limited to bottom 6 bits.
31define i32 @f3(i32 %a, i32 %sh) {
32; CHECK-LABEL: f3:
33; CHECK:       # %bb.0:
34; CHECK-NEXT:    sll %r2, 0(%r3)
35; CHECK-NEXT:    br %r14
36  %and = and i32 %sh, 255
37  %shift = shl i32 %a, %and
38  ret i32 %shift
39}
40
41; Test removal of AND mask from SRA.
42define i32 @f4(i32 %a, i32 %sh) {
43; CHECK-LABEL: f4:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    sra %r2, 0(%r3)
46; CHECK-NEXT:    br %r14
47  %and = and i32 %sh, 63
48  %shift = ashr i32 %a, %and
49  ret i32 %shift
50}
51
52; Test removal of AND mask from SRL.
53define i32 @f5(i32 %a, i32 %sh) {
54; CHECK-LABEL: f5:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    srl %r2, 0(%r3)
57; CHECK-NEXT:    br %r14
58  %and = and i32 %sh, 63
59  %shift = lshr i32 %a, %and
60  ret i32 %shift
61}
62
63; Test removal of AND mask from SLLG.
64define i64 @f6(i64 %a, i64 %sh) {
65; CHECK-LABEL: f6:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    sllg %r2, %r2, 0(%r3)
68; CHECK-NEXT:    br %r14
69  %and = and i64 %sh, 63
70  %shift = shl i64 %a, %and
71  ret i64 %shift
72}
73
74; Test removal of AND mask from SRAG.
75define i64 @f7(i64 %a, i64 %sh) {
76; CHECK-LABEL: f7:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    srag %r2, %r2, 0(%r3)
79; CHECK-NEXT:    br %r14
80  %and = and i64 %sh, 63
81  %shift = ashr i64 %a, %and
82  ret i64 %shift
83}
84
85; Test removal of AND mask from SRLG.
86define i64 @f8(i64 %a, i64 %sh) {
87; CHECK-LABEL: f8:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    srlg %r2, %r2, 0(%r3)
90; CHECK-NEXT:    br %r14
91  %and = and i64 %sh, 63
92  %shift = lshr i64 %a, %and
93  ret i64 %shift
94}
95
96; Test that AND with two register operands is not affected.
97define i32 @f9(i32 %a, i32 %b, i32 %sh) {
98; CHECK-LABEL: f9:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    nr %r3, %r4
101; CHECK-NEXT:    sll %r2, 0(%r3)
102; CHECK-NEXT:    br %r14
103  %and = and i32 %sh, %b
104  %shift = shl i32 %a, %and
105  ret i32 %shift
106}
107
108; Test that AND is not entirely removed if the result is reused.
109define i32 @f10(i32 %a, i32 %sh) {
110; CHECK-LABEL: f10:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    sll %r2, 0(%r3)
113; CHECK-NEXT:    nilf %r3, 63
114; CHECK-NEXT:    ar %r2, %r3
115; CHECK-NEXT:    br %r14
116  %and = and i32 %sh, 63
117  %shift = shl i32 %a, %and
118  %reuse = add i32 %and, %shift
119  ret i32 %reuse
120}
121
122define i128 @f11(i128 %a, i32 %sh) {
123; CHECK-LABEL: f11:
124; CHECK:       # %bb.0:
125; CHECK-NEXT:    vlvgp %v1, %r4, %r4
126; CHECK-NEXT:    vl %v0, 0(%r3), 3
127; CHECK-NEXT:    vrepb %v1, %v1, 15
128; CHECK-NEXT:    vslb %v0, %v0, %v1
129; CHECK-NEXT:    vsl %v0, %v0, %v1
130; CHECK-NEXT:    vst %v0, 0(%r2), 3
131; CHECK-NEXT:    br %r14
132  %and = and i32 %sh, 127
133  %ext = zext i32 %and to i128
134  %shift = shl i128 %a, %ext
135  ret i128 %shift
136}
137
138define i128 @f12(i128 %a, i32 %sh) {
139; CHECK-LABEL: f12:
140; CHECK:       # %bb.0:
141; CHECK-NEXT:    vlvgp %v1, %r4, %r4
142; CHECK-NEXT:    vl %v0, 0(%r3), 3
143; CHECK-NEXT:    vrepb %v1, %v1, 15
144; CHECK-NEXT:    vsrlb %v0, %v0, %v1
145; CHECK-NEXT:    vsrl %v0, %v0, %v1
146; CHECK-NEXT:    vst %v0, 0(%r2), 3
147; CHECK-NEXT:    br %r14
148  %and = and i32 %sh, 127
149  %ext = zext i32 %and to i128
150  %shift = lshr i128 %a, %ext
151  ret i128 %shift
152}
153
154define i128 @f13(i128 %a, i32 %sh) {
155; CHECK-LABEL: f13:
156; CHECK:       # %bb.0:
157; CHECK-NEXT:    vlvgp %v1, %r4, %r4
158; CHECK-NEXT:    vl %v0, 0(%r3), 3
159; CHECK-NEXT:    vrepb %v1, %v1, 15
160; CHECK-NEXT:    vsrab %v0, %v0, %v1
161; CHECK-NEXT:    vsra %v0, %v0, %v1
162; CHECK-NEXT:    vst %v0, 0(%r2), 3
163; CHECK-NEXT:    br %r14
164  %and = and i32 %sh, 127
165  %ext = zext i32 %and to i128
166  %shift = ashr i128 %a, %ext
167  ret i128 %shift
168}
169
170