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/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	combine-insert-vec-elt.mir	194 %3:_(s8) = G_CONSTANT i8 127 195 …s8>) = G_BUILD_VECTOR %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s… 196 %4:_(s8) = G_CONSTANT i8 -128 199 %1:_(<32 x s8>) = G_INSERT_VECTOR_ELT %2, %4(s8), %5(s64) 200 G_STORE %1(<32 x s8>), %0(p0) :: (store (<32 x s8>)) 213 %3:_(s8) = G_CONSTANT i8 127 214 …s8>) = G_BUILD_VECTOR %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s… 215 %4:_(s8) = G_CONSTANT i8 -128 218 %1:_(<32 x s8>) = G_INSERT_VECTOR_ELT %2, %4(s8), %5(s64) 219 G_STORE %1(<32 x s8>), %0(p0) :: (store (<32 x s8>)) [all …]
H A D	combine-shufflevector.mir	17 ; CHECK-NEXT: %a:_(<4 x s8>) = G_LOAD %p4(p0) :: (load (<4 x s8>)) 18 ; CHECK-NEXT: %b:_(<4 x s8>) = G_LOAD %p3(p0) :: (load (<4 x s8>)) 19 ; CHECK-NEXT: %c:_(<4 x s8>) = G_LOAD %p2(p0) :: (load (<4 x s8>)) 20 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s8>) = G_IMPLICIT_DEF 21 …; CHECK-NEXT: %z:_(<16 x s8>) = G_CONCAT_VECTORS %a(<4 x s8>), %b(<4 x s8>), %c(<4 x s8>), [[DEF]]… 22 ; CHECK-NEXT: $q0 = COPY %z(<16 x s8>) 29 %ImpDef:_(<4 x s8>) = G_IMPLICIT_DEF 30 %a:_(<4 x s8>) = G_LOAD %p4:_(p0) :: (load (<4 x s8>)) 31 %b:_(<4 x s8>) = G_LOAD %p3:_(p0) :: (load (<4 x s8>)) 32 %c:_(<4 x s8>) = G_LOAD %p2:_(p0) :: (load (<4 x s8>)) [all …]
H A D	legalize-build-vector.mir	`70 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF 71 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF 72 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF [all...]`
H A D	prelegalizercombiner-extending-loads-cornercases.mir	`78 %2:_(s8) = G_LOAD %0 :: (load (s8) from %ir.addr) 87 %10:_(s8) = G_CONSTANT i8 1 88 ; CHECK: [[T1:%[0-9]+]]:_(s8) = G_TRUNC [[T0]](s32) 89 %6:_(s8) = G_ADD %2, %10 90 ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_ADD [[T1]], {{.*}} 95 %11:_(s8) = G_CONSTANT i8 1 96 ; CHECK: [[T3:%[0-9]+]]:_(s8) = G_TRUNC [[T0]](s32) 97 %7:_(s8) = G_SUB %2, %11 98 ; CHECK: [[T4:%[0-9]+]]:_(s8) [all...]`
H A D	regbankselect-build-vector.mir	46 ; CHECK: [[C:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 4 47 ; CHECK: [[C1:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 10 48 ; CHECK: [[C2:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 3 49 ; CHECK: [[C3:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 11 50 ; CHECK: [[C4:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 15 51 ; CHECK: [[C5:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 44 52 ; CHECK: [[C6:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 22 53 ; CHECK: [[C7:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 19 54 ; CHECK: [[C8:%[0-9]+]]:gpr(s8) = G_CONSTANT i8 55 55 …s8>) = G_BUILD_VECTOR [[C]](s8), [[C1]](s8), [[C2]](s8), [[C3]](s8), [[C4]](s8), [[C]](s8), [[C1]]… [all …]
H A D	legalize-insert-vector-elt.mir	`41 %0:_(<2 x s8>) = G_TRUNC %1(<2 x s32>) 43 %3:_(s8) = G_CONSTANT i8 1 44 %2:_(<2 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s64) 45 %5:_(<2 x s32>) = G_ANYEXT %2(<2 x s8>) 64 %0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>) 66 %3:_(s8) = G_CONSTANT i8 1 67 %2:_(<4 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s64) 68 %5:_(<4 x s16>) = G_ANYEXT %2(<4 x s8>) [all...]`
H A D	postlegalizer-lowering-trn.mir	19 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 20 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 21 ; CHECK: [[TRN1_:%[0-9]+]]:_(<8 x s8>) = G_TRN1 [[COPY]], [[COPY1]] 22 ; CHECK: $d0 = COPY [[TRN1_]](<8 x s8>) 24 %0:_(<8 x s8>) = COPY $d0 25 %1:_(<8 x s8>) = COPY $d1 26 %2:_(<8 x s8>) = G_SHUFFLE_VECTOR %0(<8 x s8>), %1, shufflemask(0, 8, 2, 10, 4, 12, 6, 14) 27 $d0 = COPY %2(<8 x s8>) 41 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 42 ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 [all …]
H A D	legalize-select.mir	`83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 84 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 85 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 86 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[ [all...]`
H A D	legalize-sub.mir	`71 %2:_(s8) = G_TRUNC %0(s64) 72 %3:_(s8) = G_TRUNC %1(s64) 73 %4:_(s8) = G_SUB %2, %3 74 %5:_(s64) = G_ANYEXT %4(s8) 103 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 104 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 105 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[COPY]], [[COPY]] 106 ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s8>) = G_SUB [[COPY1]], [[COPY1]] 107 ; CHECK-NEXT: $q0 = COPY [[SUB]](<16 x s8>) 108 ; CHECK-NEXT: $q1 = COPY [[SUB1]](<16 x s8>) [all …]`
H A D	legalize-reduce-or.mir	101 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 102 …s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [… 103 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8) 104 ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8) 106 ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8) 107 ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8) 109 ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8) 110 ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8) 112 ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8) 113 ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8) [all …]
H A D	postlegalizer-lowering-unmerge-ext.mir	59 ; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0 60 ; CHECK-NEXT: %unused:_(<8 x s8>), %unmerge:_(<8 x s8>) = G_UNMERGE_VALUES %v1(<16 x s8>) 61 ; CHECK-NEXT: %fpext:_(<8 x s16>) = G_FPEXT %unmerge(<8 x s8>) 64 %v1:_(<16 x s8>) = COPY $q0 65 %implicit:_(<16 x s8>) = G_IMPLICIT_DEF 67 %ext:_(<16 x s8>) = G_EXT %v1:_, %implicit:_, %C:_(s32) 68 %unmerge:_(<8 x s8>), %unused:_(<8 x s8>) = G_UNMERGE_VALUES %ext:_(<16 x s8>) 69 %fpext:_(<8 x s16>) = G_FPEXT %unmerge:_(<8 x s8>) 82 ; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0 83 ; CHECK-NEXT: %implicit:_(<16 x s8>) = G_IMPLICIT_DEF [all …]
H A D	postlegalizer-lowering-ext.mir	`18 ; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0 19 ; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1 21 ; CHECK-NEXT: %shuf:_(<8 x s8>) = G_EXT %v1, %v2, [[C]](s32) 22 ; CHECK-NEXT: $d0 = COPY %shuf(<8 x s8>) 24 %v1:_(<8 x s8>) = COPY $d0 25 %v2:_(<8 x s8>) = COPY $d1 26 %shuf:_(<8 x s8>) = G_SHUFFLE_VECTOR %v1(<8 x s8>), %v2, shufflemask(3, 4, 5, 6, 7, 8, 9, 10) 27 $d0 = COPY %shuf(<8 x s8>) 41 ; CHECK-NEXT: %v1:_(<8 x s8>) = COPY $d0 42 ; CHECK-NEXT: %v2:_(<8 x s8>) = COPY $d1 [all …]`
H A D	legalize-or.mir	`19 %2:_(s8) = G_TRUNC %0 20 %3:_(s8) = G_TRUNC %1 21 %4:_(s8) = G_OR %2, %3 128 ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 129 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 130 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY]], [[COPY]] 131 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY1]], [[COPY1]] 132 ; CHECK-NEXT: $q0 = COPY [[OR]](<16 x s8>) 133 ; CHECK-NEXT: $q1 = COPY [[OR1]](<16 x s8>) 134 %0:_(<16 x s8>) = COPY $q0 [all …]`
H A D	prelegalizercombiner-extending-loads.mir	12 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8)) 15 %1:_(s8) = G_LOAD %0 :: (load (s8)) 29 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8)) 32 %1:_(s8) = G_LOAD %0 :: (load (s8)) 33 %2:_(s8) = COPY %1 47 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) 50 %1:_(s8) = G_LOAD %0 :: (load (s8)) 64 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) 67 %1:_(s8) = G_LOAD %0 :: (load (s8)) 81 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8)) [all …]
H A D	legalize-reduce-xor.mir	105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 106 …s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [… 107 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8) 108 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8) 110 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8) 111 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8) 113 ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8) 114 ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8) 116 ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8) 117 ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8) [all …]
H A D	legalize-reduce-and.mir	105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 106 …s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [… 107 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8) 108 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8) 110 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8) 111 ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8) 113 ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8) 114 ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8) 116 ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8) 117 ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8) [all …]
H A D	postlegalizer-lowering-build-vector-to-dup.mir	`15 ; LOWER-NEXT: %r:_(s8) = G_IMPLICIT_DEF 16 ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_DUP %r(s8) 17 ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>) 27 %r:_(s8) = G_IMPLICIT_DEF 28 %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r, %r, %r, %r, %r, %r, %r, %r 29 $d0 = COPY %build_vector(<8 x s8>) 88 ; LOWER-NEXT: %r:_(s8) = G_CONSTANT i8 0 89 ; LOWER-NEXT: %build_vector:_(<8 x s8>) = G_BUILD_VECTOR %r(s8), [all...]`
/llvm-project/llvm/unittests/CodeGen/GlobalISel/
H A D	KnownBitsVectorTest.cpp	`16 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8)) in TEST_F() 17 %mask0:_(s8) = G_CONSTANT i8 24 in TEST_F() 18 %mask1:_(s8) = G_CONSTANT i8 224 in TEST_F() 19 %tmp0:_(s8) = G_AND %unknown, %mask0 in TEST_F() 20 %val0:_(s8) = G_OR %tmp0, %mask1 in TEST_F() 21 %mask2:_(s8) = G_CONSTANT i8 146 in TEST_F() 22 %mask3:_(s8) = G_CONSTANT i8 36 in TEST_F() 23 %tmp1:_(s8) = G_AND %unknown, %mask2 in TEST_F() 24 %val1:_(s8) in TEST_F() [all...]`
H A D	KnownBitsTest.cpp	14 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n" in TEST_F() 15 " %4:_(s8) = COPY %3\n"; in TEST_F() 63 " %10:_(s8) = G_CONSTANT i8 3\n" in TEST_F() 69 " %12:_(s8) = G_CONSTANT i8 2\n" in TEST_F() 73 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11\n" in TEST_F() 74 " %14:_(s8) = COPY %13\n"; in TEST_F() 103 " %12:_(s8) = G_CONSTANT i8 2\n" in TEST_F() 107 " %13:_(s8) = PHI %10, %bb.10, %12(s8), %bb.11\n" in TEST_F() 108 " %14:_(s8) = COPY %13\n"; in TEST_F() 171 " %10:_(s8) = G_CONSTANT i8 3\n" in TEST_F() [all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A D	zcmp-prolog-epilog-crash.mir	66 ; CHECK-NEXT: SB $x0, $x2, 31 :: (store (s8) into %stack.0 + 31) 67 ; CHECK-NEXT: SB $x0, $x2, 30 :: (store (s8) into %stack.0 + 30) 68 ; CHECK-NEXT: SB $x0, $x2, 29 :: (store (s8) into %stack.0 + 29) 69 ; CHECK-NEXT: SB $x0, $x2, 28 :: (store (s8) into %stack.0 + 28) 70 ; CHECK-NEXT: SB $x0, $x2, 27 :: (store (s8) into %stack.0 + 27) 71 ; CHECK-NEXT: SB $x0, $x2, 26 :: (store (s8) into %stack.0 + 26) 72 ; CHECK-NEXT: SB $x0, $x2, 25 :: (store (s8) into %stack.0 + 25) 73 ; CHECK-NEXT: SB $x0, $x2, 24 :: (store (s8) into %stack.0 + 24) 74 ; CHECK-NEXT: SB $x0, $x2, 23 :: (store (s8) into %stack.0 + 23) 75 ; CHECK-NEXT: SB $x0, $x2, 22 :: (store (s8) int [all...]
/llvm-project/llvm/test/CodeGen/X86/GlobalISel/
H A D	legalize-add-v512.mir	50 ; AVX1-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 51 ; AVX1-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 52 …]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>), [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16… 53 …]]:_(<16 x s8>), [[UV5:%[0-9]+]]:_(<16 x s8>), [[UV6:%[0-9]+]]:_(<16 x s8>), [[UV7:%[0-9]+]]:_(<16… 54 ; AVX1-NEXT: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV4]] 55 ; AVX1-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV5]] 56 ; AVX1-NEXT: [[ADD2:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV2]], [[UV6]] 57 ; AVX1-NEXT: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]] 58 …ECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>), [[ADD2]]… 59 ; AVX1-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>) [all …]
H A D	legalize-and-v512.mir	49 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 50 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 51 …; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<… 52 …; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]]… 53 ; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[UV]], [[UV2]] 54 ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<32 x s8>) = G_AND [[UV1]], [[UV3]] 55 … AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[AND]](<32 x s8>), [[AND1]]… 56 ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>) 61 ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 62 ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF [all …]
H A D	legalize-or-v512.mir	49 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 50 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 51 …; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<… 52 …; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]]… 53 ; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[UV]], [[UV2]] 54 ; AVX-NEXT: [[OR1:%[0-9]+]]:_(<32 x s8>) = G_OR [[UV1]], [[UV3]] 55 …; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[OR]](<32 x s8>), [[OR1]](… 56 ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>) 61 ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 62 ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF [all …]
H A D	legalize-xor-v512.mir	49 ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 50 ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 51 …; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<… 52 …; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]]… 53 ; AVX-NEXT: [[XOR:%[0-9]+]]:_(<32 x s8>) = G_XOR [[UV]], [[UV2]] 54 ; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<32 x s8>) = G_XOR [[UV1]], [[UV3]] 55 … AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[XOR]](<32 x s8>), [[XOR1]]… 56 ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>) 61 ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF 62 ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF [all …]
/llvm-project/llvm/test/CodeGen/Thumb2/
H A D	mve-fmas.ll	`21 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8 23 ; CHECK-MVE-NEXT: vmla.f16 s0, s4, s8 27 ; CHECK-MVE-NEXT: vmovx.f16 s8, s5 28 ; CHECK-MVE-NEXT: vmla.f16 s12, s8, s4 33 ; CHECK-MVE-NEXT: vmovx.f16 s8, s6 34 ; CHECK-MVE-NEXT: vmla.f16 s12, s8, s4 36 ; CHECK-MVE-NEXT: vmovx.f16 s8, s3 40 ; CHECK-MVE-NEXT: vmla.f16 s8, s6, s4 43 ; CHECK-MVE-NEXT: vins.f16 s3, s8 66 ; CHECK-MVE-NEXT: vmovx.f16 s12, s8 [all...]`

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