xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-and.mir (revision 873d2aff426b484a7934c6b43a533a718d8bfbb1) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            test_redand_v1i1
6alignment:       4
7tracksRegLiveness: true
8liveins:
9  - { reg: '$w0' }
10body:             |
11  bb.1:
12    liveins: $w0
13
14    ; CHECK-LABEL: name: test_redand_v1i1
15    ; CHECK: liveins: $w0
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
18    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
19    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
20    ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
21    ; CHECK-NEXT: RET_ReallyLR implicit $w0
22    %1:_(s32) = COPY $w0
23    %0:_(s1) = G_TRUNC %1(s32)
24    %2:_(s1) = G_VECREDUCE_AND %0(s1)
25    %4:_(s32) = G_ZEXT %2(s1)
26    $w0 = COPY %4(s32)
27    RET_ReallyLR implicit $w0
28
29...
30---
31name:            test_redand_v2i1
32alignment:       4
33tracksRegLiveness: true
34liveins:
35  - { reg: '$d0' }
36body:             |
37  bb.1:
38    liveins: $d0
39
40    ; CHECK-LABEL: name: test_redand_v2i1
41    ; CHECK: liveins: $d0
42    ; CHECK-NEXT: {{  $}}
43    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
44    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
45    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV1]]
46    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
47    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
48    ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
49    ; CHECK-NEXT: RET_ReallyLR implicit $w0
50    %1:_(<2 x s32>) = COPY $d0
51    %0:_(<2 x s1>) = G_TRUNC %1(<2 x s32>)
52    %2:_(s1) = G_VECREDUCE_AND %0(<2 x s1>)
53    %4:_(s32) = G_ZEXT %2(s1)
54    $w0 = COPY %4(s32)
55    RET_ReallyLR implicit $w0
56
57...
58---
59name:            test_redand_v4i1
60alignment:       4
61tracksRegLiveness: true
62liveins:
63  - { reg: '$d0' }
64body:             |
65  bb.1:
66    liveins: $d0
67
68    ; CHECK-LABEL: name: test_redand_v4i1
69    ; CHECK: liveins: $d0
70    ; CHECK-NEXT: {{  $}}
71    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
72    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
73    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
74    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
75    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
76    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
77    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
78    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
79    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]]
80    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
81    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[AND2]], [[C]]
82    ; CHECK-NEXT: $w0 = COPY [[AND3]](s32)
83    ; CHECK-NEXT: RET_ReallyLR implicit $w0
84    %1:_(<4 x s16>) = COPY $d0
85    %0:_(<4 x s1>) = G_TRUNC %1(<4 x s16>)
86    %2:_(s1) = G_VECREDUCE_AND %0(<4 x s1>)
87    %4:_(s32) = G_ZEXT %2(s1)
88    $w0 = COPY %4(s32)
89    RET_ReallyLR implicit $w0
90
91...
92---
93name:            test_redand_v8i1
94alignment:       4
95tracksRegLiveness: true
96liveins:
97  - { reg: '$d0' }
98body:             |
99  bb.1:
100    liveins: $d0
101
102    ; CHECK-LABEL: name: test_redand_v8i1
103    ; CHECK: liveins: $d0
104    ; CHECK-NEXT: {{  $}}
105    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
106    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
107    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
108    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
109    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
110    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
111    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
112    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
113    ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
114    ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
115    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]
116    ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
117    ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
118    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]
119    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]]
120    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[AND2]], [[AND3]]
121    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[AND4]], [[AND5]]
122    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
123    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[AND6]], [[C]]
124    ; CHECK-NEXT: $w0 = COPY [[AND7]](s32)
125    ; CHECK-NEXT: RET_ReallyLR implicit $w0
126    %1:_(<8 x s8>) = COPY $d0
127    %0:_(<8 x s1>) = G_TRUNC %1(<8 x s8>)
128    %2:_(s1) = G_VECREDUCE_AND %0(<8 x s1>)
129    %4:_(s32) = G_ZEXT %2(s1)
130    $w0 = COPY %4(s32)
131    RET_ReallyLR implicit $w0
132
133...
134---
135name:            test_redand_v16i1
136alignment:       4
137tracksRegLiveness: true
138liveins:
139  - { reg: '$q0' }
140frameInfo:
141  maxAlignment:    1
142machineFunctionInfo: {}
143body:             |
144  bb.1:
145    liveins: $q0
146
147    ; CHECK-LABEL: name: test_redand_v16i1
148    ; CHECK: liveins: $q0
149    ; CHECK-NEXT: {{  $}}
150    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
151    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<16 x s8>)
152    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
153    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
154    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
155    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
156    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
157    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
158    ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
159    ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
160    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]
161    ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
162    ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
163    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]
164    ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
165    ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
166    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT8]], [[ANYEXT9]]
167    ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[UV10]](s8)
168    ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[UV11]](s8)
169    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT10]], [[ANYEXT11]]
170    ; CHECK-NEXT: [[ANYEXT12:%[0-9]+]]:_(s32) = G_ANYEXT [[UV12]](s8)
171    ; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[UV13]](s8)
172    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT12]], [[ANYEXT13]]
173    ; CHECK-NEXT: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[UV14]](s8)
174    ; CHECK-NEXT: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[UV15]](s8)
175    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT14]], [[ANYEXT15]]
176    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]]
177    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[AND2]], [[AND3]]
178    ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[AND4]], [[AND5]]
179    ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s32) = G_AND [[AND6]], [[AND7]]
180    ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s32) = G_AND [[AND8]], [[AND9]]
181    ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s32) = G_AND [[AND10]], [[AND11]]
182    ; CHECK-NEXT: [[AND14:%[0-9]+]]:_(s32) = G_AND [[AND12]], [[AND13]]
183    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
184    ; CHECK-NEXT: [[AND15:%[0-9]+]]:_(s32) = G_AND [[AND14]], [[C]]
185    ; CHECK-NEXT: $w0 = COPY [[AND15]](s32)
186    ; CHECK-NEXT: RET_ReallyLR implicit $w0
187    %1:_(<16 x s8>) = COPY $q0
188    %0:_(<16 x s1>) = G_TRUNC %1(<16 x s8>)
189    %2:_(s1) = G_VECREDUCE_AND %0(<16 x s1>)
190    %4:_(s32) = G_ZEXT %2(s1)
191    $w0 = COPY %4(s32)
192    RET_ReallyLR implicit $w0
193
194...
195---
196name:            test_redand_v1i8
197alignment:       4
198tracksRegLiveness: true
199liveins:
200  - { reg: '$d0' }
201body:             |
202  bb.1:
203    liveins: $d0
204
205    ; CHECK-LABEL: name: test_redand_v1i8
206    ; CHECK: liveins: $d0
207    ; CHECK-NEXT: {{  $}}
208    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
209    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[COPY]](<8 x s8>)
210    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[BITCAST]](s64)
211    ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
212    ; CHECK-NEXT: RET_ReallyLR implicit $w0
213    %1:_(<8 x s8>) = COPY $d0
214    %11:_(s64) = G_BITCAST %1(<8 x s8>)
215    %0:_(s8) = G_TRUNC %11(s64)
216    %9:_(s8) = G_VECREDUCE_AND %0(s8)
217    %10:_(s32) = G_ANYEXT %9(s8)
218    $w0 = COPY %10(s32)
219    RET_ReallyLR implicit $w0
220
221...
222---
223name:            test_redand_v3i8
224alignment:       4
225tracksRegLiveness: true
226liveins:
227  - { reg: '$w0' }
228  - { reg: '$w1' }
229  - { reg: '$w2' }
230body:             |
231  bb.1:
232    liveins: $w0, $w1, $w2
233
234    ; CHECK-LABEL: name: test_redand_v3i8
235    ; CHECK: liveins: $w0, $w1, $w2
236    ; CHECK-NEXT: {{  $}}
237    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
238    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
239    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
240    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
241    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[COPY2]]
242    ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
243    ; CHECK-NEXT: RET_ReallyLR implicit $w0
244    %1:_(s32) = COPY $w0
245    %2:_(s32) = COPY $w1
246    %3:_(s32) = COPY $w2
247    %4:_(<3 x s32>) = G_BUILD_VECTOR %1(s32), %2(s32), %3(s32)
248    %0:_(<3 x s8>) = G_TRUNC %4(<3 x s32>)
249    %5:_(s8) = G_VECREDUCE_AND %0(<3 x s8>)
250    %6:_(s32) = G_ANYEXT %5(s8)
251    $w0 = COPY %6(s32)
252    RET_ReallyLR implicit $w0
253
254...
255---
256name:            test_redand_v4i8
257alignment:       4
258tracksRegLiveness: true
259liveins:
260  - { reg: '$d0' }
261body:             |
262  bb.1:
263    liveins: $d0
264
265    ; CHECK-LABEL: name: test_redand_v4i8
266    ; CHECK: liveins: $d0
267    ; CHECK-NEXT: {{  $}}
268    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
269    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
270    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
271    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
272    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
273    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
274    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
275    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
276    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]]
277    ; CHECK-NEXT: $w0 = COPY [[AND2]](s32)
278    ; CHECK-NEXT: RET_ReallyLR implicit $w0
279    %1:_(<4 x s16>) = COPY $d0
280    %0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>)
281    %2:_(s8) = G_VECREDUCE_AND %0(<4 x s8>)
282    %3:_(s32) = G_ANYEXT %2(s8)
283    $w0 = COPY %3(s32)
284    RET_ReallyLR implicit $w0
285
286...
287---
288name:            test_redand_v8i8
289alignment:       4
290tracksRegLiveness: true
291liveins:
292  - { reg: '$d0' }
293body:             |
294  bb.1:
295    liveins: $d0
296
297    ; CHECK-LABEL: name: test_redand_v8i8
298    ; CHECK: liveins: $d0
299    ; CHECK-NEXT: {{  $}}
300    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
301    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
302    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
303    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
304    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
305    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
306    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
307    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
308    ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
309    ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
310    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]
311    ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
312    ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
313    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]
314    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]]
315    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[AND2]], [[AND3]]
316    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[AND4]], [[AND5]]
317    ; CHECK-NEXT: $w0 = COPY [[AND6]](s32)
318    ; CHECK-NEXT: RET_ReallyLR implicit $w0
319    %0:_(<8 x s8>) = COPY $d0
320    %1:_(s8) = G_VECREDUCE_AND %0(<8 x s8>)
321    %2:_(s32) = G_ANYEXT %1(s8)
322    $w0 = COPY %2(s32)
323    RET_ReallyLR implicit $w0
324
325...
326---
327name:            test_redand_v16i8
328alignment:       4
329tracksRegLiveness: true
330liveins:
331  - { reg: '$q0' }
332body:             |
333  bb.1:
334    liveins: $q0
335
336    ; CHECK-LABEL: name: test_redand_v16i8
337    ; CHECK: liveins: $q0
338    ; CHECK-NEXT: {{  $}}
339    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
340    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<8 x s8>), [[UV1:%[0-9]+]]:_(<8 x s8>) = G_UNMERGE_VALUES [[COPY]](<16 x s8>)
341    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s8>) = G_AND [[UV]], [[UV1]]
342    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[AND]](<8 x s8>)
343    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
344    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
345    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
346    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
347    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
348    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
349    ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
350    ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
351    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]
352    ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
353    ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
354    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]
355    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[AND2]]
356    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[AND3]], [[AND4]]
357    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[AND5]], [[AND6]]
358    ; CHECK-NEXT: $w0 = COPY [[AND7]](s32)
359    ; CHECK-NEXT: RET_ReallyLR implicit $w0
360    %0:_(<16 x s8>) = COPY $q0
361    %1:_(s8) = G_VECREDUCE_AND %0(<16 x s8>)
362    %2:_(s32) = G_ANYEXT %1(s8)
363    $w0 = COPY %2(s32)
364    RET_ReallyLR implicit $w0
365
366...
367---
368name:            test_redand_v32i8
369alignment:       4
370tracksRegLiveness: true
371liveins:
372  - { reg: '$q0' }
373  - { reg: '$q1' }
374body:             |
375  bb.1:
376    liveins: $q0, $q1
377
378    ; CHECK-LABEL: name: test_redand_v32i8
379    ; CHECK: liveins: $q0, $q1
380    ; CHECK-NEXT: {{  $}}
381    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
382    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
383    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY]], [[COPY1]]
384    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<8 x s8>), [[UV1:%[0-9]+]]:_(<8 x s8>) = G_UNMERGE_VALUES [[AND]](<16 x s8>)
385    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<8 x s8>) = G_AND [[UV]], [[UV1]]
386    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[AND1]](<8 x s8>)
387    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
388    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
389    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
390    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
391    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
392    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
393    ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
394    ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
395    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[ANYEXT5]]
396    ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
397    ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
398    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[ANYEXT7]]
399    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[AND2]], [[AND3]]
400    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[AND4]], [[AND5]]
401    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[AND6]], [[AND7]]
402    ; CHECK-NEXT: $w0 = COPY [[AND8]](s32)
403    ; CHECK-NEXT: RET_ReallyLR implicit $w0
404    %1:_(<16 x s8>) = COPY $q0
405    %2:_(<16 x s8>) = COPY $q1
406    %0:_(<32 x s8>) = G_CONCAT_VECTORS %1(<16 x s8>), %2(<16 x s8>)
407    %3:_(s8) = G_VECREDUCE_AND %0(<32 x s8>)
408    %4:_(s32) = G_ANYEXT %3(s8)
409    $w0 = COPY %4(s32)
410    RET_ReallyLR implicit $w0
411
412...
413---
414name:            test_redand_v4i16
415alignment:       4
416tracksRegLiveness: true
417liveins:
418  - { reg: '$d0' }
419body:             |
420  bb.1:
421    liveins: $d0
422
423    ; CHECK-LABEL: name: test_redand_v4i16
424    ; CHECK: liveins: $d0
425    ; CHECK-NEXT: {{  $}}
426    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
427    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
428    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
429    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
430    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
431    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
432    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
433    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
434    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[AND1]]
435    ; CHECK-NEXT: $w0 = COPY [[AND2]](s32)
436    ; CHECK-NEXT: RET_ReallyLR implicit $w0
437    %0:_(<4 x s16>) = COPY $d0
438    %1:_(s16) = G_VECREDUCE_AND %0(<4 x s16>)
439    %2:_(s32) = G_ANYEXT %1(s16)
440    $w0 = COPY %2(s32)
441    RET_ReallyLR implicit $w0
442
443...
444---
445name:            test_redand_v8i16
446alignment:       4
447tracksRegLiveness: true
448liveins:
449  - { reg: '$q0' }
450body:             |
451  bb.1:
452    liveins: $q0
453
454    ; CHECK-LABEL: name: test_redand_v8i16
455    ; CHECK: liveins: $q0
456    ; CHECK-NEXT: {{  $}}
457    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
458    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
459    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[UV]], [[UV1]]
460    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[AND]](<4 x s16>)
461    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
462    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
463    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
464    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
465    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
466    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
467    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[AND2]]
468    ; CHECK-NEXT: $w0 = COPY [[AND3]](s32)
469    ; CHECK-NEXT: RET_ReallyLR implicit $w0
470    %0:_(<8 x s16>) = COPY $q0
471    %1:_(s16) = G_VECREDUCE_AND %0(<8 x s16>)
472    %2:_(s32) = G_ANYEXT %1(s16)
473    $w0 = COPY %2(s32)
474    RET_ReallyLR implicit $w0
475
476...
477---
478name:            test_redand_v16i16
479alignment:       4
480tracksRegLiveness: true
481liveins:
482  - { reg: '$q0' }
483  - { reg: '$q1' }
484body:             |
485  bb.1:
486    liveins: $q0, $q1
487
488    ; CHECK-LABEL: name: test_redand_v16i16
489    ; CHECK: liveins: $q0, $q1
490    ; CHECK-NEXT: {{  $}}
491    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
492    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
493    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY]], [[COPY1]]
494    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[AND]](<8 x s16>)
495    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<4 x s16>) = G_AND [[UV]], [[UV1]]
496    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[AND1]](<4 x s16>)
497    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
498    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
499    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[ANYEXT1]]
500    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
501    ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
502    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[ANYEXT3]]
503    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND2]], [[AND3]]
504    ; CHECK-NEXT: $w0 = COPY [[AND4]](s32)
505    ; CHECK-NEXT: RET_ReallyLR implicit $w0
506    %1:_(<8 x s16>) = COPY $q0
507    %2:_(<8 x s16>) = COPY $q1
508    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
509    %3:_(s16) = G_VECREDUCE_AND %0(<16 x s16>)
510    %4:_(s32) = G_ANYEXT %3(s16)
511    $w0 = COPY %4(s32)
512    RET_ReallyLR implicit $w0
513
514...
515---
516name:            test_redand_v2i32
517alignment:       4
518tracksRegLiveness: true
519liveins:
520  - { reg: '$d0' }
521body:             |
522  bb.1:
523    liveins: $d0
524
525    ; CHECK-LABEL: name: test_redand_v2i32
526    ; CHECK: liveins: $d0
527    ; CHECK-NEXT: {{  $}}
528    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
529    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
530    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV1]]
531    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
532    ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
533    ; CHECK-NEXT: RET_ReallyLR implicit $w0
534    %0:_(<2 x s32>) = COPY $d0
535    %1:_(s32) = G_VECREDUCE_AND %0(<2 x s32>)
536    $w0 = COPY %1(s32)
537    RET_ReallyLR implicit $w0
538
539...
540---
541name:            test_redand_v4i32
542alignment:       4
543tracksRegLiveness: true
544liveins:
545  - { reg: '$q0' }
546body:             |
547  bb.1:
548    liveins: $q0
549
550    ; CHECK-LABEL: name: test_redand_v4i32
551    ; CHECK: liveins: $q0
552    ; CHECK-NEXT: {{  $}}
553    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
554    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
555    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[UV]], [[UV1]]
556    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](<2 x s32>)
557    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV3]]
558    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
559    ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
560    ; CHECK-NEXT: RET_ReallyLR implicit $w0
561    %0:_(<4 x s32>) = COPY $q0
562    %1:_(s32) = G_VECREDUCE_AND %0(<4 x s32>)
563    $w0 = COPY %1(s32)
564    RET_ReallyLR implicit $w0
565
566...
567---
568name:            test_redand_v8i32
569alignment:       4
570tracksRegLiveness: true
571liveins:
572  - { reg: '$q0' }
573  - { reg: '$q1' }
574body:             |
575  bb.1:
576    liveins: $q0, $q1
577
578    ; CHECK-LABEL: name: test_redand_v8i32
579    ; CHECK: liveins: $q0, $q1
580    ; CHECK-NEXT: {{  $}}
581    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
582    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
583    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[COPY]], [[COPY1]]
584    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[AND]](<4 x s32>)
585    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[UV]], [[UV1]]
586    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](<2 x s32>)
587    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV3]]
588    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
589    ; CHECK-NEXT: $w0 = COPY [[COPY2]](s32)
590    ; CHECK-NEXT: RET_ReallyLR implicit $w0
591    %1:_(<4 x s32>) = COPY $q0
592    %2:_(<4 x s32>) = COPY $q1
593    %0:_(<8 x s32>) = G_CONCAT_VECTORS %1(<4 x s32>), %2(<4 x s32>)
594    %3:_(s32) = G_VECREDUCE_AND %0(<8 x s32>)
595    $w0 = COPY %3(s32)
596    RET_ReallyLR implicit $w0
597
598...
599---
600name:            test_redand_v2i64
601alignment:       4
602tracksRegLiveness: true
603liveins:
604  - { reg: '$q0' }
605body:             |
606  bb.1:
607    liveins: $q0
608
609    ; CHECK-LABEL: name: test_redand_v2i64
610    ; CHECK: liveins: $q0
611    ; CHECK-NEXT: {{  $}}
612    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
613    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
614    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[UV1]]
615    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
616    ; CHECK-NEXT: $x0 = COPY [[COPY1]](s64)
617    ; CHECK-NEXT: RET_ReallyLR implicit $x0
618    %0:_(<2 x s64>) = COPY $q0
619    %1:_(s64) = G_VECREDUCE_AND %0(<2 x s64>)
620    $x0 = COPY %1(s64)
621    RET_ReallyLR implicit $x0
622
623...
624---
625name:            test_redand_v4i64
626alignment:       4
627tracksRegLiveness: true
628liveins:
629  - { reg: '$q0' }
630  - { reg: '$q1' }
631body:             |
632  bb.1:
633    liveins: $q0, $q1
634
635    ; CHECK-LABEL: name: test_redand_v4i64
636    ; CHECK: liveins: $q0, $q1
637    ; CHECK-NEXT: {{  $}}
638    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
639    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
640    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[COPY]], [[COPY1]]
641    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[AND]](<2 x s64>)
642    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[UV1]]
643    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
644    ; CHECK-NEXT: $x0 = COPY [[COPY2]](s64)
645    ; CHECK-NEXT: RET_ReallyLR implicit $x0
646    %1:_(<2 x s64>) = COPY $q0
647    %2:_(<2 x s64>) = COPY $q1
648    %0:_(<4 x s64>) = G_CONCAT_VECTORS %1(<2 x s64>), %2(<2 x s64>)
649    %3:_(s64) = G_VECREDUCE_AND %0(<4 x s64>)
650    $x0 = COPY %3(s64)
651    RET_ReallyLR implicit $x0
652
653...
654