xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir (revision 873d2aff426b484a7934c6b43a533a718d8bfbb1) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            test_redor_v1i1
6alignment:       4
7tracksRegLiveness: true
8liveins:
9  - { reg: '$w0' }
10body:             |
11  bb.1:
12    liveins: $w0
13
14    ; CHECK-LABEL: name: test_redor_v1i1
15    ; CHECK: liveins: $w0
16    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
17    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
18    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
19    ; CHECK: $w0 = COPY [[AND]](s32)
20    ; CHECK: RET_ReallyLR implicit $w0
21    %1:_(s32) = COPY $w0
22    %0:_(s1) = G_TRUNC %1(s32)
23    %2:_(s1) = G_VECREDUCE_OR %0(s1)
24    %4:_(s32) = G_ZEXT %2(s1)
25    $w0 = COPY %4(s32)
26    RET_ReallyLR implicit $w0
27
28...
29---
30name:            test_redor_v2i1
31alignment:       4
32tracksRegLiveness: true
33liveins:
34  - { reg: '$d0' }
35body:             |
36  bb.1:
37    liveins: $d0
38
39    ; CHECK-LABEL: name: test_redor_v2i1
40    ; CHECK: liveins: $d0
41    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
42    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
43    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV1]]
44    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
45    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]]
46    ; CHECK: $w0 = COPY [[AND]](s32)
47    ; CHECK: RET_ReallyLR implicit $w0
48    %1:_(<2 x s32>) = COPY $d0
49    %0:_(<2 x s1>) = G_TRUNC %1(<2 x s32>)
50    %2:_(s1) = G_VECREDUCE_OR %0(<2 x s1>)
51    %4:_(s32) = G_ZEXT %2(s1)
52    $w0 = COPY %4(s32)
53    RET_ReallyLR implicit $w0
54
55...
56---
57name:            test_redor_v4i1
58alignment:       4
59tracksRegLiveness: true
60liveins:
61  - { reg: '$d0' }
62body:             |
63  bb.1:
64    liveins: $d0
65
66    ; CHECK-LABEL: name: test_redor_v4i1
67    ; CHECK: liveins: $d0
68    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
69    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
70    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
71    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
72    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
73    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
74    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
75    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
76    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
77    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
78    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C]]
79    ; CHECK: $w0 = COPY [[AND]](s32)
80    ; CHECK: RET_ReallyLR implicit $w0
81    %1:_(<4 x s16>) = COPY $d0
82    %0:_(<4 x s1>) = G_TRUNC %1(<4 x s16>)
83    %2:_(s1) = G_VECREDUCE_OR %0(<4 x s1>)
84    %4:_(s32) = G_ZEXT %2(s1)
85    $w0 = COPY %4(s32)
86    RET_ReallyLR implicit $w0
87
88...
89---
90name:            test_redor_v8i1
91alignment:       4
92tracksRegLiveness: true
93liveins:
94  - { reg: '$d0' }
95body:             |
96  bb.1:
97    liveins: $d0
98
99    ; CHECK-LABEL: name: test_redor_v8i1
100    ; CHECK: liveins: $d0
101    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
102    ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
103    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
104    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
105    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
106    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
107    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
108    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
109    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
110    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
111    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT4]], [[ANYEXT5]]
112    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
113    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
114    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
115    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
116    ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
117    ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
118    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
119    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR6]], [[C]]
120    ; CHECK: $w0 = COPY [[AND]](s32)
121    ; CHECK: RET_ReallyLR implicit $w0
122    %1:_(<8 x s8>) = COPY $d0
123    %0:_(<8 x s1>) = G_TRUNC %1(<8 x s8>)
124    %2:_(s1) = G_VECREDUCE_OR %0(<8 x s1>)
125    %4:_(s32) = G_ZEXT %2(s1)
126    $w0 = COPY %4(s32)
127    RET_ReallyLR implicit $w0
128
129...
130---
131name:            test_redor_v16i1
132alignment:       4
133tracksRegLiveness: true
134liveins:
135  - { reg: '$q0' }
136frameInfo:
137  maxAlignment:    1
138machineFunctionInfo: {}
139body:             |
140  bb.1:
141    liveins: $q0
142
143    ; CHECK-LABEL: name: test_redor_v16i1
144    ; CHECK: liveins: $q0
145    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
146    ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8), [[UV12:%[0-9]+]]:_(s8), [[UV13:%[0-9]+]]:_(s8), [[UV14:%[0-9]+]]:_(s8), [[UV15:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<16 x s8>)
147    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
148    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
149    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
150    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
151    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
152    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
153    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
154    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
155    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT4]], [[ANYEXT5]]
156    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
157    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
158    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
159    ; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
160    ; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
161    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ANYEXT8]], [[ANYEXT9]]
162    ; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[UV10]](s8)
163    ; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[UV11]](s8)
164    ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ANYEXT10]], [[ANYEXT11]]
165    ; CHECK: [[ANYEXT12:%[0-9]+]]:_(s32) = G_ANYEXT [[UV12]](s8)
166    ; CHECK: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[UV13]](s8)
167    ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ANYEXT12]], [[ANYEXT13]]
168    ; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[UV14]](s8)
169    ; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[UV15]](s8)
170    ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ANYEXT14]], [[ANYEXT15]]
171    ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
172    ; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
173    ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
174    ; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[OR7]]
175    ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[OR9]]
176    ; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[OR11]]
177    ; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[OR13]]
178    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
179    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR14]], [[C]]
180    ; CHECK: $w0 = COPY [[AND]](s32)
181    ; CHECK: RET_ReallyLR implicit $w0
182    %1:_(<16 x s8>) = COPY $q0
183    %0:_(<16 x s1>) = G_TRUNC %1(<16 x s8>)
184    %2:_(s1) = G_VECREDUCE_OR %0(<16 x s1>)
185    %4:_(s32) = G_ZEXT %2(s1)
186    $w0 = COPY %4(s32)
187    RET_ReallyLR implicit $w0
188
189...
190---
191name:            test_redor_v1i8
192alignment:       4
193tracksRegLiveness: true
194liveins:
195  - { reg: '$d0' }
196body:             |
197  bb.1:
198    liveins: $d0
199
200    ; CHECK-LABEL: name: test_redor_v1i8
201    ; CHECK: liveins: $d0
202    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
203    ; CHECK: [[BITCAST:%[0-9]+]]:_(s64) = G_BITCAST [[COPY]](<8 x s8>)
204    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[BITCAST]](s64)
205    ; CHECK: $w0 = COPY [[TRUNC]](s32)
206    ; CHECK: RET_ReallyLR implicit $w0
207    %1:_(<8 x s8>) = COPY $d0
208    %11:_(s64) = G_BITCAST %1(<8 x s8>)
209    %0:_(s8) = G_TRUNC %11(s64)
210    %9:_(s8) = G_VECREDUCE_OR %0(s8)
211    %10:_(s32) = G_ANYEXT %9(s8)
212    $w0 = COPY %10(s32)
213    RET_ReallyLR implicit $w0
214
215...
216---
217name:            test_redor_v3i8
218alignment:       4
219tracksRegLiveness: true
220liveins:
221  - { reg: '$w0' }
222  - { reg: '$w1' }
223  - { reg: '$w2' }
224body:             |
225  bb.1:
226    liveins: $w0, $w1, $w2
227
228    ; CHECK-LABEL: name: test_redor_v3i8
229    ; CHECK: liveins: $w0, $w1, $w2
230    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
231    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
232    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
233    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
234    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[COPY2]]
235    ; CHECK: $w0 = COPY [[OR1]](s32)
236    ; CHECK: RET_ReallyLR implicit $w0
237    %1:_(s32) = COPY $w0
238    %2:_(s32) = COPY $w1
239    %3:_(s32) = COPY $w2
240    %4:_(<3 x s32>) = G_BUILD_VECTOR %1(s32), %2(s32), %3(s32)
241    %0:_(<3 x s8>) = G_TRUNC %4(<3 x s32>)
242    %5:_(s8) = G_VECREDUCE_OR %0(<3 x s8>)
243    %6:_(s32) = G_ANYEXT %5(s8)
244    $w0 = COPY %6(s32)
245    RET_ReallyLR implicit $w0
246
247...
248---
249name:            test_redor_v4i8
250alignment:       4
251tracksRegLiveness: true
252liveins:
253  - { reg: '$d0' }
254body:             |
255  bb.1:
256    liveins: $d0
257
258    ; CHECK-LABEL: name: test_redor_v4i8
259    ; CHECK: liveins: $d0
260    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
261    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
262    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
263    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
264    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
265    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
266    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
267    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
268    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
269    ; CHECK: $w0 = COPY [[OR2]](s32)
270    ; CHECK: RET_ReallyLR implicit $w0
271    %1:_(<4 x s16>) = COPY $d0
272    %0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>)
273    %2:_(s8) = G_VECREDUCE_OR %0(<4 x s8>)
274    %3:_(s32) = G_ANYEXT %2(s8)
275    $w0 = COPY %3(s32)
276    RET_ReallyLR implicit $w0
277
278...
279---
280name:            test_redor_v8i8
281alignment:       4
282tracksRegLiveness: true
283liveins:
284  - { reg: '$d0' }
285body:             |
286  bb.1:
287    liveins: $d0
288
289    ; CHECK-LABEL: name: test_redor_v8i8
290    ; CHECK: liveins: $d0
291    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
292    ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
293    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
294    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
295    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
296    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
297    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
298    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
299    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
300    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
301    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT4]], [[ANYEXT5]]
302    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
303    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
304    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
305    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
306    ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
307    ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
308    ; CHECK: $w0 = COPY [[OR6]](s32)
309    ; CHECK: RET_ReallyLR implicit $w0
310    %0:_(<8 x s8>) = COPY $d0
311    %1:_(s8) = G_VECREDUCE_OR %0(<8 x s8>)
312    %2:_(s32) = G_ANYEXT %1(s8)
313    $w0 = COPY %2(s32)
314    RET_ReallyLR implicit $w0
315
316...
317---
318name:            test_redor_v16i8
319alignment:       4
320tracksRegLiveness: true
321liveins:
322  - { reg: '$q0' }
323body:             |
324  bb.1:
325    liveins: $q0
326
327    ; CHECK-LABEL: name: test_redor_v16i8
328    ; CHECK: liveins: $q0
329    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
330    ; CHECK: [[UV:%[0-9]+]]:_(<8 x s8>), [[UV1:%[0-9]+]]:_(<8 x s8>) = G_UNMERGE_VALUES [[COPY]](<16 x s8>)
331    ; CHECK: [[OR:%[0-9]+]]:_(<8 x s8>) = G_OR [[UV]], [[UV1]]
332    ; CHECK: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[OR]](<8 x s8>)
333    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
334    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
335    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
336    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
337    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
338    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
339    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
340    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
341    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT4]], [[ANYEXT5]]
342    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
343    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
344    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
345    ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[OR2]]
346    ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[OR4]]
347    ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[OR6]]
348    ; CHECK: $w0 = COPY [[OR7]](s32)
349    ; CHECK: RET_ReallyLR implicit $w0
350    %0:_(<16 x s8>) = COPY $q0
351    %1:_(s8) = G_VECREDUCE_OR %0(<16 x s8>)
352    %2:_(s32) = G_ANYEXT %1(s8)
353    $w0 = COPY %2(s32)
354    RET_ReallyLR implicit $w0
355
356...
357---
358name:            test_redor_v32i8
359alignment:       4
360tracksRegLiveness: true
361liveins:
362  - { reg: '$q0' }
363  - { reg: '$q1' }
364body:             |
365  bb.1:
366    liveins: $q0, $q1
367
368    ; CHECK-LABEL: name: test_redor_v32i8
369    ; CHECK: liveins: $q0, $q1
370    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
371    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
372    ; CHECK: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[COPY]], [[COPY1]]
373    ; CHECK: [[UV:%[0-9]+]]:_(<8 x s8>), [[UV1:%[0-9]+]]:_(<8 x s8>) = G_UNMERGE_VALUES [[OR]](<16 x s8>)
374    ; CHECK: [[OR1:%[0-9]+]]:_(<8 x s8>) = G_OR [[UV]], [[UV1]]
375    ; CHECK: [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[OR1]](<8 x s8>)
376    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
377    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
378    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
379    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
380    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
381    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
382    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
383    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
384    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ANYEXT4]], [[ANYEXT5]]
385    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
386    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
387    ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
388    ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
389    ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
390    ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[OR7]]
391    ; CHECK: $w0 = COPY [[OR8]](s32)
392    ; CHECK: RET_ReallyLR implicit $w0
393    %1:_(<16 x s8>) = COPY $q0
394    %2:_(<16 x s8>) = COPY $q1
395    %0:_(<32 x s8>) = G_CONCAT_VECTORS %1(<16 x s8>), %2(<16 x s8>)
396    %3:_(s8) = G_VECREDUCE_OR %0(<32 x s8>)
397    %4:_(s32) = G_ANYEXT %3(s8)
398    $w0 = COPY %4(s32)
399    RET_ReallyLR implicit $w0
400
401...
402---
403name:            test_redor_v4i16
404alignment:       4
405tracksRegLiveness: true
406liveins:
407  - { reg: '$d0' }
408body:             |
409  bb.1:
410    liveins: $d0
411
412    ; CHECK-LABEL: name: test_redor_v4i16
413    ; CHECK: liveins: $d0
414    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
415    ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
416    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
417    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
418    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
419    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
420    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
421    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
422    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
423    ; CHECK: $w0 = COPY [[OR2]](s32)
424    ; CHECK: RET_ReallyLR implicit $w0
425    %0:_(<4 x s16>) = COPY $d0
426    %1:_(s16) = G_VECREDUCE_OR %0(<4 x s16>)
427    %2:_(s32) = G_ANYEXT %1(s16)
428    $w0 = COPY %2(s32)
429    RET_ReallyLR implicit $w0
430
431...
432---
433name:            test_redor_v8i16
434alignment:       4
435tracksRegLiveness: true
436liveins:
437  - { reg: '$q0' }
438body:             |
439  bb.1:
440    liveins: $q0
441
442    ; CHECK-LABEL: name: test_redor_v8i16
443    ; CHECK: liveins: $q0
444    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
445    ; CHECK: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
446    ; CHECK: [[OR:%[0-9]+]]:_(<4 x s16>) = G_OR [[UV]], [[UV1]]
447    ; CHECK: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR]](<4 x s16>)
448    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
449    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
450    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
451    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
452    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
453    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
454    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[OR2]]
455    ; CHECK: $w0 = COPY [[OR3]](s32)
456    ; CHECK: RET_ReallyLR implicit $w0
457    %0:_(<8 x s16>) = COPY $q0
458    %1:_(s16) = G_VECREDUCE_OR %0(<8 x s16>)
459    %2:_(s32) = G_ANYEXT %1(s16)
460    $w0 = COPY %2(s32)
461    RET_ReallyLR implicit $w0
462
463...
464---
465name:            test_redor_v16i16
466alignment:       4
467tracksRegLiveness: true
468liveins:
469  - { reg: '$q0' }
470  - { reg: '$q1' }
471body:             |
472  bb.1:
473    liveins: $q0, $q1
474
475    ; CHECK-LABEL: name: test_redor_v16i16
476    ; CHECK: liveins: $q0, $q1
477    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
478    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
479    ; CHECK: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[COPY]], [[COPY1]]
480    ; CHECK: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[OR]](<8 x s16>)
481    ; CHECK: [[OR1:%[0-9]+]]:_(<4 x s16>) = G_OR [[UV]], [[UV1]]
482    ; CHECK: [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR1]](<4 x s16>)
483    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
484    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
485    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
486    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
487    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
488    ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
489    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
490    ; CHECK: $w0 = COPY [[OR4]](s32)
491    ; CHECK: RET_ReallyLR implicit $w0
492    %1:_(<8 x s16>) = COPY $q0
493    %2:_(<8 x s16>) = COPY $q1
494    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
495    %3:_(s16) = G_VECREDUCE_OR %0(<16 x s16>)
496    %4:_(s32) = G_ANYEXT %3(s16)
497    $w0 = COPY %4(s32)
498    RET_ReallyLR implicit $w0
499
500...
501---
502name:            test_redor_v2i32
503alignment:       4
504tracksRegLiveness: true
505liveins:
506  - { reg: '$d0' }
507body:             |
508  bb.1:
509    liveins: $d0
510
511    ; CHECK-LABEL: name: test_redor_v2i32
512    ; CHECK: liveins: $d0
513    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
514    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
515    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV1]]
516    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
517    ; CHECK: $w0 = COPY [[COPY1]](s32)
518    ; CHECK: RET_ReallyLR implicit $w0
519    %0:_(<2 x s32>) = COPY $d0
520    %1:_(s32) = G_VECREDUCE_OR %0(<2 x s32>)
521    $w0 = COPY %1(s32)
522    RET_ReallyLR implicit $w0
523
524...
525---
526name:            test_redor_v4i32
527alignment:       4
528tracksRegLiveness: true
529liveins:
530  - { reg: '$q0' }
531body:             |
532  bb.1:
533    liveins: $q0
534
535    ; CHECK-LABEL: name: test_redor_v4i32
536    ; CHECK: liveins: $q0
537    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
538    ; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
539    ; CHECK: [[OR:%[0-9]+]]:_(<2 x s32>) = G_OR [[UV]], [[UV1]]
540    ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR]](<2 x s32>)
541    ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV2]], [[UV3]]
542    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
543    ; CHECK: $w0 = COPY [[COPY1]](s32)
544    ; CHECK: RET_ReallyLR implicit $w0
545    %0:_(<4 x s32>) = COPY $q0
546    %1:_(s32) = G_VECREDUCE_OR %0(<4 x s32>)
547    $w0 = COPY %1(s32)
548    RET_ReallyLR implicit $w0
549
550...
551---
552name:            test_redor_v8i32
553alignment:       4
554tracksRegLiveness: true
555liveins:
556  - { reg: '$q0' }
557  - { reg: '$q1' }
558body:             |
559  bb.1:
560    liveins: $q0, $q1
561
562    ; CHECK-LABEL: name: test_redor_v8i32
563    ; CHECK: liveins: $q0, $q1
564    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
565    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
566    ; CHECK: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[COPY]], [[COPY1]]
567    ; CHECK: [[UV:%[0-9]+]]:_(<2 x s32>), [[UV1:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[OR]](<4 x s32>)
568    ; CHECK: [[OR1:%[0-9]+]]:_(<2 x s32>) = G_OR [[UV]], [[UV1]]
569    ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[OR1]](<2 x s32>)
570    ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[UV2]], [[UV3]]
571    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
572    ; CHECK: $w0 = COPY [[COPY2]](s32)
573    ; CHECK: RET_ReallyLR implicit $w0
574    %1:_(<4 x s32>) = COPY $q0
575    %2:_(<4 x s32>) = COPY $q1
576    %0:_(<8 x s32>) = G_CONCAT_VECTORS %1(<4 x s32>), %2(<4 x s32>)
577    %3:_(s32) = G_VECREDUCE_OR %0(<8 x s32>)
578    $w0 = COPY %3(s32)
579    RET_ReallyLR implicit $w0
580
581...
582---
583name:            test_redor_v2i64
584alignment:       4
585tracksRegLiveness: true
586liveins:
587  - { reg: '$q0' }
588body:             |
589  bb.1:
590    liveins: $q0
591
592    ; CHECK-LABEL: name: test_redor_v2i64
593    ; CHECK: liveins: $q0
594    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
595    ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
596    ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[UV]], [[UV1]]
597    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
598    ; CHECK: $x0 = COPY [[COPY1]](s64)
599    ; CHECK: RET_ReallyLR implicit $x0
600    %0:_(<2 x s64>) = COPY $q0
601    %1:_(s64) = G_VECREDUCE_OR %0(<2 x s64>)
602    $x0 = COPY %1(s64)
603    RET_ReallyLR implicit $x0
604
605...
606---
607name:            test_redor_v4i64
608alignment:       4
609tracksRegLiveness: true
610liveins:
611  - { reg: '$q0' }
612  - { reg: '$q1' }
613body:             |
614  bb.1:
615    liveins: $q0, $q1
616
617    ; CHECK-LABEL: name: test_redor_v4i64
618    ; CHECK: liveins: $q0, $q1
619    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
620    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
621    ; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[COPY]], [[COPY1]]
622    ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[OR]](<2 x s64>)
623    ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[UV]], [[UV1]]
624    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR1]](s64)
625    ; CHECK: $x0 = COPY [[COPY2]](s64)
626    ; CHECK: RET_ReallyLR implicit $x0
627    %1:_(<2 x s64>) = COPY $q0
628    %2:_(<2 x s64>) = COPY $q1
629    %0:_(<4 x s64>) = G_CONCAT_VECTORS %1(<2 x s64>), %2(<2 x s64>)
630    %3:_(s64) = G_VECREDUCE_OR %0(<4 x s64>)
631    $x0 = COPY %3(s64)
632    RET_ReallyLR implicit $x0
633
634...
635