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/llvm-project/llvm/test/tools/llvm-mca/ARM/
H A Dm55-fp.s7 vadd.f16 s0, s2, s1
8 vadd.f32 s0, s2, s1
10 vcmp.f16 s1, s2
11 vcmp.f32 s1, s2
13 vcmp.f16 s1, #0.0
14 vcmp.f32 s1, #0.0
16 vcmpe.f16 s1, s2
17 vcmpe.f32 s1, s2
19 vcmpe.f16 s1, #0.0
20 vcmpe.f32 s1, #0.0
[all …]
H A Dm85-fp.s7 vadd.f16 s0, s2, s1
8 vadd.f32 s0, s2, s1
10 vcmp.f16 s1, s2
11 vcmp.f32 s1, s2
13 vcmp.f16 s1, #0.0
14 vcmp.f32 s1, #0.0
16 vcmpe.f16 s1, s2
17 vcmpe.f32 s1, s2
19 vcmpe.f16 s1, #0.0
20 vcmpe.f32 s1, #0.0
[all …]
H A Dm7-fp.s6 vadd.f32 s0, s2, s1
8 vcmp.f32 s1, s2
10 vcvt.f32.f64 s1, d2
11 vcvt.f64.f32 d1, s1
12 vcvt.f32.u16 s1, s2, #8
13 vcvt.f32.s16 s1, s2, #8
14 vcvt.f32.u32 s1, s2, #8
15 vcvt.f32.s32 s1, s2, #8
16 vcvt.u16.f32 s1, s2, #8
17 vcvt.s16.f32 s1, s2, #8
[all …]
/llvm-project/llvm/test/CodeGen/VE/Vector/
H A Dvec_broadcast.ll7 ; CHECK-NEXT: lea %s1, 256
8 ; CHECK-NEXT: lvl %s1
31 ; CHECK-NEXT: lea %s1, 256
32 ; CHECK-NEXT: lvl %s1
56 ; CHECK-NEXT: lea %s1, 256
57 ; CHECK-NEXT: lvl %s1
80 ; CHECK-NEXT: lea %s1, 256
81 ; CHECK-NEXT: lvl %s1
106 ; CHECK-NEXT: lea %s1, 256
107 ; CHECK-NEXT: lvl %s1
[all …]
H A Dstorevm.ll11 ; CHECK-NEXT: svm %s1, %vm1, 3
12 ; CHECK-NEXT: st %s1, 24(, %s0)
13 ; CHECK-NEXT: svm %s1, %vm1, 2
14 ; CHECK-NEXT: st %s1, 16(, %s0)
15 ; CHECK-NEXT: svm %s1, %vm1, 1
16 ; CHECK-NEXT: st %s1, 8(, %s0)
17 ; CHECK-NEXT: svm %s1, %vm1, 0
18 ; CHECK-NEXT: st %s1, (, %s0)
29 ; CHECK-NEXT: lea %s1, v256i1@lo
30 ; CHECK-NEXT: and %s1, %s1, (32)0
[all …]
/llvm-project/libcxx/test/std/time/time.duration/time.duration.comparisons/
H A Dop_less.pass.cpp42 std::chrono::seconds s1(3); in main() local
44 assert(!(s1 < s2)); in main()
45 assert(!(s1 > s2)); in main()
46 assert( (s1 <= s2)); in main()
47 assert( (s1 >= s2)); in main()
50 std::chrono::seconds s1(3); in main() local
52 assert( (s1 < s2)); in main()
53 assert(!(s1 > s2)); in main()
54 assert( (s1 <= s2)); in main()
55 assert(!(s1 >= s2)); in main()
[all …]
H A Dop_equal.pass.cpp32 std::chrono::seconds s1(3); in main() local
34 assert(s1 == s2); in main()
35 assert(!(s1 != s2)); in main()
38 std::chrono::seconds s1(3); in main() local
40 assert(!(s1 == s2)); in main()
41 assert(s1 != s2); in main()
44 std::chrono::milliseconds s1(3); in main() local
46 assert(s1 == s2); in main()
47 assert(!(s1 != s2)); in main()
50 std::chrono::milliseconds s1(3); in main() local
[all …]
/llvm-project/clang/test/Analysis/
H A Dpr22954.c1 // Given code 'struct aa { char s1[4]; char * s2;} a; memcpy(a.s1, ...);',
2 …t the CStringChecker only invalidates the destination buffer array a.s1 (instead of a.s1 and a.s2).
4 // If a.s1 region has a symbolic offset, the whole region of 'a' is invalidated.
18 char s1[4]; member
27 memcpy(a0.s1, input, 4); in f0()
28 clang_analyzer_eval(a0.s1[0] == 'a'); // expected-warning{{UNKNOWN}} in f0()
29 clang_analyzer_eval(a0.s1[1] == 'b'); // expected-warning{{UNKNOWN}} in f0()
30 clang_analyzer_eval(a0.s1[2] == 'c'); // expected-warning{{UNKNOWN}} in f0()
31 clang_analyzer_eval(a0.s1[3] == 'd'); // expected-warning{{UNKNOWN}} in f0()
41 memcpy(a1.s1, input, 4); in f1()
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Ddivergence-divergent-i1-used-outside-loop.mir21 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C1]]
22 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)
23 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
24 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[DEF]](s1)
25 …; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implic…
26 …; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-d…
27 …; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](…
28 ; GFX10-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
33 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %36(s1), %bb.1
34 ; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.0, %24(s1), %bb.1
[all …]
H A Dsub.v2i16.ll238 ; GFX9-NEXT: s_lshr_b32 s1, s0, 16
240 ; GFX9-NEXT: s_sub_i32 s1, s1, 0xffc0
241 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
246 ; GFX8-NEXT: s_lshr_b32 s1, s0, 16
249 ; GFX8-NEXT: s_add_i32 s1, s1, 0xffff0040
250 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
252 ; GFX8-NEXT: s_or_b32 s0, s1, s
[all...]
H A Ddivergence-structurizer.mir20 ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]
22 ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C1]]
23 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)
24 ; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[COPY4]](s1)
25 ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec
32 ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]
33 ; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)
[all...]
H A Dadd.v2i16.ll265 ; GFX7-NEXT: s_sub_i32 s1, s1, 64
267 ; GFX7-NEXT: s_and_b32 s1, s1, 0xffff
269 ; GFX7-NEXT: s_lshl_b32 s1, s1, 16
270 ; GFX7-NEXT: s_or_b32 s0, s0, s1
275 ; GFX9-NEXT: s_lshr_b32 s1, s0, 16
277 ; GFX9-NEXT: s_add_i32 s1, s1, 0xffc0
278 ; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
283 ; GFX8-NEXT: s_lshr_b32 s1, s0, 16
286 ; GFX8-NEXT: s_add_i32 s1, s1, 0xffc0
287 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
[all …]
H A Ddivergence-temporal-divergent-i1.mir18 ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
20 ; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
25 ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %22(s1), %bb.1
28 ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1
29 ; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)
30 ; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
31 ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
32 ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C2]]
34 ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]
37 …:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI1]](s32)
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/
H A Dicmp.mir16 ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF
17 …; RV32I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x…
18 ; RV32I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>)
22 ; RV64I: [[DEF:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF
23 …; RV64I-NEXT: [[ICMP:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sgt), [[DEF]](<vscale x 1 x…
24 ; RV64I-NEXT: $v8 = COPY [[ICMP]](<vscale x 1 x s1>)
26 %0:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF
27 %1:_(<vscale x 1 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 1 x s1>), %0
28 $v8 = COPY %1(<vscale x 1 x s1>)
39 ; RV32I: [[DEF:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF
[all …]
/llvm-project/llvm/test/CodeGen/VE/Scalar/
H A Dsetccf64i.ll24 ; CHECK-NEXT: lea.sl %s1, 0
25 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
26 ; CHECK-NEXT: or %s1, 0, (0)1
27 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
28 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
37 ; CHECK-NEXT: lea.sl %s1, 0
38 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
39 ; CHECK-NEXT: or %s1, 0, (0)1
40 ; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0
41 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
[all …]
H A Dsetccf32i.ll24 ; CHECK-NEXT: lea.sl %s1, 0
25 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
26 ; CHECK-NEXT: or %s1, 0, (0)1
27 ; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
28 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
37 ; CHECK-NEXT: lea.sl %s1, 0
38 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
39 ; CHECK-NEXT: or %s1, 0, (0)1
40 ; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
41 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
[all …]
H A Dsetcci32i.ll6 ; CHECK-NEXT: or %s1, 12, (0)1
7 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
8 ; CHECK-NEXT: or %s1, 0, (0)1
9 ; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
10 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
19 ; CHECK-NEXT: or %s1, 12, (0)1
20 ; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
21 ; CHECK-NEXT: or %s1, 0, (0)1
22 ; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s0
23 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
[all …]
H A Dsetcci64i.ll6 ; CHECK-NEXT: or %s1, 12, (0)1
7 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
8 ; CHECK-NEXT: or %s1, 0, (0)1
9 ; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
10 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
19 ; CHECK-NEXT: or %s1, 12, (0)1
20 ; CHECK-NEXT: cmps.l %s0, %s0, %s1
21 ; CHECK-NEXT: or %s1, 0, (0)1
22 ; CHECK-NEXT: cmov.l.ne %s1, (63)0, %s0
23 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
[all …]
H A Dsetccf32.ll24 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
25 ; CHECK-NEXT: or %s1, 0, (0)1
26 ; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
27 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
36 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
37 ; CHECK-NEXT: or %s1, 0, (0)1
38 ; CHECK-NEXT: cmov.s.ne %s1, (63)0, %s0
39 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
48 ; CHECK-NEXT: fcmp.s %s0, %s0, %s1
49 ; CHECK-NEXT: or %s1, 0, (0)1
[all …]
H A Dsetccf64.ll24 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
25 ; CHECK-NEXT: or %s1, 0, (0)1
26 ; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
27 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
36 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
37 ; CHECK-NEXT: or %s1, 0, (0)1
38 ; CHECK-NEXT: cmov.d.ne %s1, (63)0, %s0
39 ; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
48 ; CHECK-NEXT: fcmp.d %s0, %s0, %s1
49 ; CHECK-NEXT: or %s1, 0, (0)1
[all …]
/llvm-project/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_sopc.s3 s_cmp_eq_i32 s1, s2
72 s_cmp_eq_i32 s1, s103
75 s_cmp_eq_i32 s1, flat_scratch_lo
78 s_cmp_eq_i32 s1, flat_scratch_hi
81 s_cmp_eq_i32 s1, vcc_lo
84 s_cmp_eq_i32 s1, vcc_hi
87 s_cmp_eq_i32 s1, tba_lo
90 s_cmp_eq_i32 s1, tba_hi
93 s_cmp_eq_i32 s1, tma_lo
96 s_cmp_eq_i32 s1, tma_hi
[all …]
H A Dgfx8_asm_sopc.s3 s_cmp_eq_i32 s1, s2
72 s_cmp_eq_i32 s1, s101
75 s_cmp_eq_i32 s1, flat_scratch_lo
78 s_cmp_eq_i32 s1, flat_scratch_hi
81 s_cmp_eq_i32 s1, vcc_lo
84 s_cmp_eq_i32 s1, vcc_hi
87 s_cmp_eq_i32 s1, tba_lo
90 s_cmp_eq_i32 s1, tba_hi
93 s_cmp_eq_i32 s1, tma_lo
96 s_cmp_eq_i32 s1, tma_hi
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dfold-brcond-fcmp.mir19 ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
22 ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
32 ; CHECK-NEXT: $s1 = COPY %cmp_rhs
33 ; CHECK-NEXT: RET_ReallyLR implicit $s1
36 liveins: $s0, $s1, $w0, $w1
39 %cmp_rhs:fpr(s32) = COPY $s1
47 $s1 = COPY %cmp_rhs
48 RET_ReallyLR implicit $s1
60 ; CHECK-NEXT: liveins: $s0, $s1, $w0, $w1
63 ; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A Dcallee-saved-fpr64s.ll441 ; ILP32-NEXT: sw s1, 260(sp) # 4-byte Folded Spill
447 ; ILP32-NEXT: addi s1, s0, %lo(var)
448 ; ILP32-NEXT: fld fa5, 16(s1)
450 ; ILP32-NEXT: fld fa5, 24(s1)
452 ; ILP32-NEXT: fld fa5, 32(s1)
454 ; ILP32-NEXT: fld fa5, 40(s1)
456 ; ILP32-NEXT: fld fa5, 48(s1)
458 ; ILP32-NEXT: fld fa5, 56(s1)
460 ; ILP32-NEXT: fld fa5, 64(s1)
462 ; ILP32-NEXT: fld fa5, 72(s1)
[all...]
H A Dcallee-saved-fpr32s.ll709 ; ILP32-NEXT: sw s1, 132(sp) # 4-byte Folded Spill
719 ; ILP32-NEXT: addi s1, s0, %lo(var)
720 ; ILP32-NEXT: flw fa5, 16(s1)
722 ; ILP32-NEXT: flw fa5, 20(s1)
724 ; ILP32-NEXT: flw fa5, 24(s1)
726 ; ILP32-NEXT: flw fa5, 28(s1)
728 ; ILP32-NEXT: flw fa5, 32(s1)
730 ; ILP32-NEXT: flw fa5, 36(s1)
732 ; ILP32-NEXT: flw fa5, 40(s1)
734 ; ILP32-NEXT: flw fa5, 44(s1)
[all...]

12345678910>>...167