xref: /llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir (revision 8a65ee8b2a05e276ab64682c3c9d3f93490cedcc) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
3
4---
5name: temporal_divergent_i1_phi
6legalized: true
7tracksRegLiveness: true
8body: |
9  ; GFX10-LABEL: name: temporal_divergent_i1_phi
10  ; GFX10: bb.0:
11  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
12  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
13  ; GFX10-NEXT: {{  $}}
14  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
15  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
16  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
17  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
18  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
19  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
20  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
21  ; GFX10-NEXT: {{  $}}
22  ; GFX10-NEXT: bb.1:
23  ; GFX10-NEXT:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
24  ; GFX10-NEXT: {{  $}}
25  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %22(s1), %bb.1
26  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0
27  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1
28  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1
29  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)
30  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
31  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
32  ; GFX10-NEXT:   [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C2]]
33  ; GFX10-NEXT:   [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI2]](s32)
34  ; GFX10-NEXT:   [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]
35  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
36  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C3]]
37  ; GFX10-NEXT:   [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI1]](s32)
38  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY4]](s1), $exec_lo, implicit-def $scc
39  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY3]](s1), implicit-def $scc
40  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
41  ; GFX10-NEXT:   SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
42  ; GFX10-NEXT:   G_BR %bb.2
43  ; GFX10-NEXT: {{  $}}
44  ; GFX10-NEXT: bb.2:
45  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.1
46  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
47  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32)
48  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
49  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
50  ; GFX10-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY5]](s1), [[C5]], [[C4]]
51  ; GFX10-NEXT:   G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))
52  ; GFX10-NEXT:   SI_RETURN
53  bb.0:
54    successors: %bb.1(0x80000000)
55    liveins: $vgpr0, $vgpr1, $vgpr2
56
57    %0:_(s32) = COPY $vgpr0
58    %1:_(s32) = COPY $vgpr1
59    %2:_(s32) = COPY $vgpr2
60    %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32)
61    %4:_(s1) = G_CONSTANT i1 true
62    %5:_(s32) = G_CONSTANT i32 0
63
64  bb.1:
65    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
66
67    %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.0
68    %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1
69    %10:_(s1) = G_PHI %4(s1), %bb.0, %11(s1), %bb.1
70    %12:_(s1) = G_CONSTANT i1 true
71    %11:_(s1) = G_XOR %10, %12
72    %13:_(s32) = G_UITOFP %8(s32)
73    %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0
74    %15:_(s32) = G_CONSTANT i32 1
75    %9:_(s32) = G_ADD %8, %15
76    %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32)
77    SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
78    G_BR %bb.2
79
80  bb.2:
81    %16:_(s1) = G_PHI %10(s1), %bb.1
82    %17:_(s32) = G_PHI %7(s32), %bb.1
83    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32)
84    %18:_(s32) = G_FCONSTANT float 0.000000e+00
85    %19:_(s32) = G_FCONSTANT float 1.000000e+00
86    %20:_(s32) = G_SELECT %16(s1), %19, %18
87    G_STORE %20(s32), %3(p0) :: (store (s32))
88    SI_RETURN
89...
90
91---
92name: temporal_divergent_i1_non_phi
93legalized: true
94tracksRegLiveness: true
95body: |
96  ; GFX10-LABEL: name: temporal_divergent_i1_non_phi
97  ; GFX10: bb.0:
98  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
99  ; GFX10-NEXT:   liveins: $vgpr0, $vgpr1, $vgpr2
100  ; GFX10-NEXT: {{  $}}
101  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
102  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
103  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
104  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
105  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
106  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
107  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
108  ; GFX10-NEXT: {{  $}}
109  ; GFX10-NEXT: bb.1:
110  ; GFX10-NEXT:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
111  ; GFX10-NEXT: {{  $}}
112  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %22(s1), %bb.1
113  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0
114  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1
115  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1
116  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
117  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
118  ; GFX10-NEXT:   [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C2]]
119  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)
120  ; GFX10-NEXT:   [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI2]](s32)
121  ; GFX10-NEXT:   [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]
122  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
123  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C3]]
124  ; GFX10-NEXT:   [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI1]](s32)
125  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY3]](s1), $exec_lo, implicit-def $scc
126  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc
127  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
128  ; GFX10-NEXT:   SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
129  ; GFX10-NEXT:   G_BR %bb.2
130  ; GFX10-NEXT: {{  $}}
131  ; GFX10-NEXT: bb.2:
132  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.1
133  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
134  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32)
135  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
136  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
137  ; GFX10-NEXT:   [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[COPY5]](s1), [[C5]], [[C4]]
138  ; GFX10-NEXT:   G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))
139  ; GFX10-NEXT:   SI_RETURN
140  bb.0:
141    successors: %bb.1(0x80000000)
142    liveins: $vgpr0, $vgpr1, $vgpr2
143
144    %0:_(s32) = COPY $vgpr0
145    %1:_(s32) = COPY $vgpr1
146    %2:_(s32) = COPY $vgpr2
147    %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32)
148    %4:_(s1) = G_CONSTANT i1 true
149    %5:_(s32) = G_CONSTANT i32 0
150
151  bb.1:
152    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
153
154    %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.0
155    %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1
156    %10:_(s1) = G_PHI %4(s1), %bb.0, %11(s1), %bb.1
157    %12:_(s1) = G_CONSTANT i1 true
158    %11:_(s1) = G_XOR %10, %12
159    %13:_(s32) = G_UITOFP %8(s32)
160    %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0
161    %15:_(s32) = G_CONSTANT i32 1
162    %9:_(s32) = G_ADD %8, %15
163    %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32)
164    SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
165    G_BR %bb.2
166
167  bb.2:
168    %16:_(s1) = G_PHI %11(s1), %bb.1
169    %17:_(s32) = G_PHI %7(s32), %bb.1
170    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32)
171    %18:_(s32) = G_FCONSTANT float 0.000000e+00
172    %19:_(s32) = G_FCONSTANT float 1.000000e+00
173    %20:_(s32) = G_SELECT %16(s1), %19, %18
174    G_STORE %20(s32), %3(p0) :: (store (s32))
175    SI_RETURN
176...
177
178---
179name: loop_with_1break
180legalized: true
181tracksRegLiveness: true
182body: |
183  ; GFX10-LABEL: name: loop_with_1break
184  ; GFX10: bb.0:
185  ; GFX10-NEXT:   successors: %bb.1(0x80000000)
186  ; GFX10-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2
187  ; GFX10-NEXT: {{  $}}
188  ; GFX10-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
189  ; GFX10-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
190  ; GFX10-NEXT:   [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
191  ; GFX10-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
192  ; GFX10-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0
193  ; GFX10-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr1
194  ; GFX10-NEXT:   [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
195  ; GFX10-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr2
196  ; GFX10-NEXT:   [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr3
197  ; GFX10-NEXT:   [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY5]](s32), [[COPY6]](s32)
198  ; GFX10-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
199  ; GFX10-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
200  ; GFX10-NEXT:   [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
201  ; GFX10-NEXT:   [[DEF2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = IMPLICIT_DEF
202  ; GFX10-NEXT: {{  $}}
203  ; GFX10-NEXT: bb.1:
204  ; GFX10-NEXT:   successors: %bb.3(0x50000000), %bb.5(0x30000000)
205  ; GFX10-NEXT: {{  $}}
206  ; GFX10-NEXT:   [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = PHI [[DEF2]](s1), %bb.0, %53(s1), %bb.5
207  ; GFX10-NEXT:   [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %42(s1), %bb.5
208  ; GFX10-NEXT:   [[PHI2:%[0-9]+]]:_(s32) = G_PHI %13(s32), %bb.5, [[C]](s32), %bb.0
209  ; GFX10-NEXT:   [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %15(s32), %bb.5
210  ; GFX10-NEXT:   [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI]](s1)
211  ; GFX10-NEXT:   [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
212  ; GFX10-NEXT:   [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
213  ; GFX10-NEXT:   [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[C1]](s1)
214  ; GFX10-NEXT:   [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI3]](s32)
215  ; GFX10-NEXT:   [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
216  ; GFX10-NEXT:   [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32)
217  ; GFX10-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)
218  ; GFX10-NEXT:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)
219  ; GFX10-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
220  ; GFX10-NEXT:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]]
221  ; GFX10-NEXT:   [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY8]](s1), $exec_lo, implicit-def $scc
222  ; GFX10-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY9]](s1), implicit-def $scc
223  ; GFX10-NEXT:   [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
224  ; GFX10-NEXT:   [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)
225  ; GFX10-NEXT:   G_BRCOND [[ICMP]](s1), %bb.3
226  ; GFX10-NEXT:   G_BR %bb.5
227  ; GFX10-NEXT: {{  $}}
228  ; GFX10-NEXT: bb.2:
229  ; GFX10-NEXT:   successors: %bb.4(0x80000000)
230  ; GFX10-NEXT: {{  $}}
231  ; GFX10-NEXT:   [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
232  ; GFX10-NEXT:   G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1)
233  ; GFX10-NEXT:   G_BR %bb.4
234  ; GFX10-NEXT: {{  $}}
235  ; GFX10-NEXT: bb.3:
236  ; GFX10-NEXT:   successors: %bb.5(0x80000000)
237  ; GFX10-NEXT: {{  $}}
238  ; GFX10-NEXT:   [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
239  ; GFX10-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
240  ; GFX10-NEXT:   [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C6]](s32)
241  ; GFX10-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64)
242  ; GFX10-NEXT:   [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)
243  ; GFX10-NEXT:   [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
244  ; GFX10-NEXT:   [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C7]]
245  ; GFX10-NEXT:   G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1)
246  ; GFX10-NEXT:   [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C7]]
247  ; GFX10-NEXT:   [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI3]](s32), [[COPY2]]
248  ; GFX10-NEXT:   [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP1]](s1)
249  ; GFX10-NEXT:   [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
250  ; GFX10-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc
251  ; GFX10-NEXT:   [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc
252  ; GFX10-NEXT:   G_BR %bb.5
253  ; GFX10-NEXT: {{  $}}
254  ; GFX10-NEXT: bb.4:
255  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32)
256  ; GFX10-NEXT:   S_ENDPGM 0
257  ; GFX10-NEXT: {{  $}}
258  ; GFX10-NEXT: bb.5:
259  ; GFX10-NEXT:   successors: %bb.6(0x04000000), %bb.1(0x7c000000)
260  ; GFX10-NEXT: {{  $}}
261  ; GFX10-NEXT:   [[PHI4:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, [[S_OR_B32_1]](s1), %bb.3
262  ; GFX10-NEXT:   [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1
263  ; GFX10-NEXT:   [[PHI6:%[0-9]+]]:_(s1) = G_PHI [[C5]](s1), %bb.3, [[C1]](s1), %bb.1
264  ; GFX10-NEXT:   [[COPY12:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[PHI6]](s1)
265  ; GFX10-NEXT:   [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[PHI4]](s1)
266  ; GFX10-NEXT:   [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY13]](s1), [[PHI2]](s32)
267  ; GFX10-NEXT:   [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_ANDN2_B32 [[COPY7]](s1), $exec_lo, implicit-def $scc
268  ; GFX10-NEXT:   [[S_AND_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_AND_B32 $exec_lo, [[COPY12]](s1), implicit-def $scc
269  ; GFX10-NEXT:   [[S_OR_B32_2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc
270  ; GFX10-NEXT:   SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
271  ; GFX10-NEXT:   G_BR %bb.6
272  ; GFX10-NEXT: {{  $}}
273  ; GFX10-NEXT: bb.6:
274  ; GFX10-NEXT:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
275  ; GFX10-NEXT: {{  $}}
276  ; GFX10-NEXT:   [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[INT]](s32), %bb.5
277  ; GFX10-NEXT:   [[COPY14:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[S_OR_B32_2]](s1)
278  ; GFX10-NEXT:   G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI7]](s32)
279  ; GFX10-NEXT:   [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY14]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
280  ; GFX10-NEXT:   G_BR %bb.2
281  bb.0:
282    successors: %bb.1(0x80000000)
283    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2
284
285    %0:_(s32) = COPY $vgpr0
286    %1:_(s32) = COPY $vgpr1
287    %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
288    %3:_(s32) = COPY $vgpr2
289    %4:_(s32) = COPY $sgpr0
290    %5:_(s32) = COPY $sgpr1
291    %6:_(p1) = G_MERGE_VALUES %4(s32), %5(s32)
292    %7:_(s32) = COPY $sgpr2
293    %8:_(s32) = COPY $sgpr3
294    %9:_(p1) = G_MERGE_VALUES %7(s32), %8(s32)
295    %10:_(s32) = G_CONSTANT i32 0
296    %11:_(s32) = G_IMPLICIT_DEF
297
298  bb.1:
299    successors: %bb.3(0x50000000), %bb.5(0x30000000)
300
301    %12:_(s32) = G_PHI %13(s32), %bb.5, %10(s32), %bb.0
302    %14:_(s32) = G_PHI %10(s32), %bb.0, %15(s32), %bb.5
303    %16:_(s1) = G_CONSTANT i1 true
304    %17:_(s64) = G_SEXT %14(s32)
305    %18:_(s32) = G_CONSTANT i32 2
306    %19:_(s64) = G_SHL %17, %18(s32)
307    %20:_(p1) = G_PTR_ADD %6, %19(s64)
308    %21:_(s32) = G_LOAD %20(p1) :: (load (s32), addrspace 1)
309    %22:_(s32) = G_CONSTANT i32 0
310    %23:_(s1) = G_ICMP intpred(ne), %21(s32), %22
311    G_BRCOND %23(s1), %bb.3
312    G_BR %bb.5
313
314  bb.2:
315    successors: %bb.4(0x80000000)
316
317    %24:_(s32) = G_CONSTANT i32 10
318    G_STORE %24(s32), %9(p1) :: (store (s32), addrspace 1)
319    G_BR %bb.4
320
321  bb.3:
322    successors: %bb.5(0x80000000)
323
324    %25:_(s1) = G_CONSTANT i1 false
325    %26:_(s32) = G_CONSTANT i32 2
326    %27:_(s64) = G_SHL %17, %26(s32)
327    %28:_(p1) = G_PTR_ADD %2, %27(s64)
328    %29:_(s32) = G_LOAD %28(p1) :: (load (s32), addrspace 1)
329    %30:_(s32) = G_CONSTANT i32 1
330    %31:_(s32) = G_ADD %29, %30
331    G_STORE %31(s32), %28(p1) :: (store (s32), addrspace 1)
332    %32:_(s32) = G_ADD %14, %30
333    %33:_(s1) = G_ICMP intpred(ult), %14(s32), %3
334    G_BR %bb.5
335
336  bb.4:
337    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32)
338    S_ENDPGM 0
339
340  bb.5:
341    successors: %bb.6(0x04000000), %bb.1(0x7c000000)
342
343    %15:_(s32) = G_PHI %32(s32), %bb.3, %11(s32), %bb.1
344    %35:_(s1) = G_PHI %25(s1), %bb.3, %16(s1), %bb.1
345    %36:_(s1) = G_PHI %33(s1), %bb.3, %16(s1), %bb.1
346    %13:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %36(s1), %12(s32)
347    SI_LOOP %13(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
348    G_BR %bb.6
349
350  bb.6:
351    successors: %bb.2(0x40000000), %bb.4(0x40000000)
352
353    %37:sreg_32_xm0_xexec(s1) = G_PHI %35(s1), %bb.5
354    %38:_(s32) = G_PHI %13(s32), %bb.5
355    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %38(s32)
356    %34:sreg_32_xm0_xexec(s32) = SI_IF %37(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec
357    G_BR %bb.2
358...
359