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Searched +full:phy +full:- +full:input +full:- +full:delay +full:- +full:legacy (Results 1 – 25 of 36) sorted by relevance

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/freebsd-src/sys/contrib/device-tree/Bindings/mmc/
H A Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
34 # PHY DLL input delays:
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H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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/freebsd-src/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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H A Dnvidia,tegra20-usb-phy.txt1 Tegra SOC USB PHY
3 The device node for Tegra SOC USB PHY:
6 - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
7 For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
8 "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
10 - reg : Defines the following set of registers, in the order listed:
11 - The PHY's own register set.
13 - The register set of the PHY containing the UTMI pad control registers.
14 Present if-and-only-if phy_type == utmi.
15 - phy_type : Should be one of "utmi", "ulpi" or "hsic".
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/freebsd-src/sys/contrib/device-tree/src/arm64/amd/
H A Delba.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
6 #include <dt-bindings/gpio/gpio.h>
7 #include "dt-bindings/interrupt-controlle
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/freebsd-src/sys/contrib/device-tree/src/arm64/socionext/
H A Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
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H A Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
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H A Duniphier-ld11.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 compatible = "socionext,uniphier-ld11";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
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/freebsd-src/sys/dev/e1000/
H A Dif_em.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
40 static const char em_driver_version[] = "7.7.8-fbsd";
41 static const char igb_driver_version[] = "2.5.28-fbsd";
55 /* Intel(R) - lem-clas
4925 static int input = 3; /* default is full */ em_set_flowcntl() local
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H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
177 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
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/freebsd-src/sys/dev/bxe/
H A Dbxe_elink.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
757 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
948 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
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/freebsd-src/sys/dev/iwm/
H A Dif_iwmreg.h10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
73 * BEGIN iwl-csr.h
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
109 * 31-16: Reserved
110 * 15-
2966 uint32_t phy; global() member
2984 uint32_t phy; global() member
5405 uint16_t delay; global() member
5571 uint32_t delay; global() member
5882 uint16_t delay; global() member
5901 uint16_t delay; global() member
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/freebsd-src/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include "rk3399-base.dtsi"
9 cluster0_opp: opp-table-0 {
10 compatible = "operating-points-v2";
11 opp-share
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/freebsd-src/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
48 #define AR_CFG_PHOK 0x00000100 // PHY OK status
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
124 #define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame
238 #define AR_ISR_HP_RXOK 0x00000001 // At least one frame rx on high-priority queue sans errors
239 #define AR_ISR_LP_RXOK 0x00000002 // At least one frame rx on low-priority queue sans errors
249 #define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC
251 #define AR_ISR_RXPHY 0x00004000 // PHY receive error interrupt
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/freebsd-src/sys/dev/igc/
H A Dif_igc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
6 * Copyright (c) 2021-2024 Rubicon Communications, LLC (Netgate)
51 /* Intel(R) PRO/1000 Network Connection - igc */
53 "Intel(R) Ethernet Controller I225-LM"),
55 "Intel(R) Ethernet Controller I225-
2787 static int input = 3; /* default is full */ igc_set_flowcntl() local
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/freebsd-src/sys/dev/ixgbe/
H A Dixgbe_type.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * - IXGBE_ERROR_INVALID_STATE
48 * - IXGBE_ERROR_POLLING
53 * - IXGBE_ERROR_CAUTION
58 * - IXGBE_ERROR_SOFTWARE
64 * - IXGBE_ERROR_ARGUMEN
4214 struct ixgbe_phy_info phy; global() member
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H A Dixgbe_common.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
64 * ixgbe_init_ops_generic - Inits function ptrs
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_generic()
72 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_generic()
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; in ixgbe_init_ops_generic()
81 eeprom->op in ixgbe_init_ops_generic()
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/freebsd-src/sys/dev/ath/ath_hal/
H A Dah.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
61 const char *name = (*pchip)->probe(vendorid, devid); in ath_hal_probe()
68 const char *name = pc->probe(vendorid, devid); in ath_hal_probe()
97 if (chip->probe(ATHEROS_VENDOR_ID, devid) == AH_NULL) in ath_hal_attach()
99 ah = chip->attach(devid, sc, st, sh, eepromdata, ah_config, in ath_hal_attach()
103 ah->ah_devid = AH_PRIVATE(ah)->ah_devid; in ath_hal_attach()
104 ah->ah_subvendorid = AH_PRIVATE(ah)->ah_subvendorid; in ath_hal_attach()
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/freebsd-src/sys/dev/bce/
H A Dif_bce.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006-2014 QLogic Corporation
42 * BCM5706C A0, A1 (pre-production)
43 * BCM5706S A0, A1 (pre-production)
44 * BCM5708C A0, B0 (pre-production)
45 * BCM5708S A0, B0 (pre-productio
1824 bce_miibus_read_reg(device_t dev,int phy,int reg) bce_miibus_read_reg() argument
1902 bce_miibus_write_reg(device_t dev,int phy,int reg,int val) bce_miibus_write_reg() argument
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/freebsd-src/sys/dev/isci/scil/
H A Dscic_sds_controller.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
97 * The number of milliseconds to wait for a phy to start.
102 * The number of milliseconds to wait while a given phy is consuming
133 (((U32)(SMU_CQGR_CYCLE_BIT & (x))) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
154 (controller)->completion_queue_entries, \
167 (controller)->completion_event_entries, \
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/freebsd-src/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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/freebsd-src/sys/dev/ice/
H A Dice_common.c1 /* SPDX-License-Identifier: BSD-3-Clause */
127 * ice_dump_phy_type - helper function to dump phy_type in ice_dump_phy_type()
158 * ice_set_mac_type - Sets MAC type in ice_set_mac_type()
168 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) in ice_set_mac_type()
171 switch (hw->device_id) { in ice_set_mac_type()
178 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
199 hw->mac_typ in ice_set_mac_type()
1997 u32 delay = ICE_RES_POLLING_DELAY_MS; ice_acquire_res() local
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H A Dice_lib.c1 /* SPDX-License-Identifier: BSD-3-Clause */
267 * ice_map_bar - Map PCIe BAR memory in ice_map_bar()
278 if (bar->res != NULL) { in ice_map_bar()
283 bar->rid = PCIR_BAR(bar_num);
284 bar->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &bar->rid,
286 if (!bar->re
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/freebsd-src/sys/conf/
H A DNOTES2 # NOTES -- Lines that can be cut/pasted into kernel and hints configs.
11 # Please use ``make LINT'' to create an old-style LINT file if you want to
12 # do kernel test-builds.
48 # auto-size based on physical memory.
66 # after most other flags. Here we use it to inhibit use of non-optimal
67 # gcc built-in functions (e.g., memcmp).
70 # The following is equivalent to 'config -g KERNELNAME' and creates
71 # 'kernel.debug' compiled with -g debugging as well as a normal
81 makeoptions CONF_CFLAGS=-fn
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/freebsd-src/sys/dev/ath/ath_hal/ar5416/
H A Dar5416_reset.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
37 /* Additional Time delay to wait after activiting the Base band */
122 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); in ar5416Reset()
144 * Don't do this for the AR9285 - it breaks RX for single in ar5416Reset()
173 (ah->ah_config.ah_force_full_reset)) in ar5416Reset()
176 /* Mark PHY as inactive; marked active in ar5416InitBB() */ in ar5416Reset()
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