Lines Matching +full:phy +full:- +full:input +full:- +full:delay +full:- +full:legacy
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2001-2024, Intel Corporation
40 static const char em_driver_version[] = "7.7.8-fbsd";
41 static const char igb_driver_version[] = "2.5.28-fbsd";
55 /* Intel(R) - lem-class legacy devices */
57 "Intel(R) Legacy PRO/1000 MT 82540EM"),
59 "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
61 "Intel(R) Legacy PRO/1000 MT 82540EP"),
63 "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
65 "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
68 "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
70 "Intel(R) Legacy PRO/1000 82541ER"),
72 "Intel(R) Legacy PRO/1000 MT 82541ER"),
74 "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
76 "Intel(R) Legacy PRO/1000 MT 82541GI"),
78 "Intel(R) Legacy PRO/1000 GT 82541PI"),
80 "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
83 "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
86 "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
88 "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
91 "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
93 "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
95 "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
97 "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
100 "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
102 "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
104 "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
106 "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
108 "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
111 "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
113 "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
115 "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
117 "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
119 "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
121 "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
123 "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
125 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
127 "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
130 "Intel(R) Legacy PRO/1000 CT 82547EI"),
132 "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
134 "Intel(R) Legacy PRO/1000 CT 82547GI"),
136 /* Intel(R) - em-class devices */
185 PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
189 "Intel(R) 82566DM-2 ICH9 AMT"),
190 PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
193 PVID(0x8086, E1000_DEV_ID_ICH9_IFE, "Intel(R) 82562V-2 ICH9"),
194 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_GT, "Intel(R) 82562GT-2 ICH9"),
195 PVID(0x8086, E1000_DEV_ID_ICH9_IFE_G, "Intel(R) 82562G-2 ICH9"),
196 PVID(0x8086, E1000_DEV_ID_ICH9_BM, "Intel(R) 82567LM-4 ICH9"),
198 PVID(0x8086, E1000_DEV_ID_82574LA, "Intel(R) 82574L-Apple"),
199 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LM, "Intel(R) 82567LM-2 ICH10"),
200 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_LF, "Intel(R) 82567LF-2 ICH10"),
201 PVID(0x8086, E1000_DEV_ID_ICH10_R_BM_V, "Intel(R) 82567V-2 ICH10"),
202 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LM, "Intel(R) 82567LM-3 ICH10"),
203 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_LF, "Intel(R) 82567LF-3 ICH10"),
204 PVID(0x8086, E1000_DEV_ID_ICH10_D_BM_V, "Intel(R) 82567V-4 ICH10"),
211 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
212 PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
214 "Intel(R) I218-LM LPTLP"),
215 PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
216 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
217 PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
218 PVID(0x8086, E1000_DEV_ID_PCH_I218_LM3, "Intel(R) I218-LM (3)"),
219 PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
220 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
221 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
223 "Intel(R) I219-LM SPT-H(2)"),
225 "Intel(R) I219-V SPT-H(2)"),
227 "Intel(R) I219-LM LBG(3)"),
229 "Intel(R) I219-LM SPT(4)"),
230 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
232 "Intel(R) I219-LM SPT(5)"),
233 PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
235 "Intel(R) I219-LM CNP(6)"),
236 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
238 "Intel(R) I219-LM CNP(7)"),
239 PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
241 "Intel(R) I219-LM ICP(8)"),
242 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
244 "Intel(R) I219-LM ICP(9)"),
245 PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
247 "Intel(R) I219-LM CMP(10)"),
249 "Intel(R) I219-V CMP(10)"),
251 "Intel(R) I219-LM CMP(11)"),
253 "Intel(R) I219-V CMP(11)"),
255 "Intel(R) I219-LM CMP(12)"),
257 "Intel(R) I219-V CMP(12)"),
259 "Intel(R) I219-LM TGP(13)"),
261 "Intel(R) I219-V TGP(13)"),
263 "Intel(R) I219-LM TGP(14)"),
265 "Intel(R) I219-V GTP(14)"),
267 "Intel(R) I219-LM TGP(15)"),
269 "Intel(R) I219-V TGP(15)"),
271 "Intel(R) I219-LM ADL(16)"),
273 "Intel(R) I219-V ADL(16)"),
275 "Intel(R) I219-LM ADL(17)"),
277 "Intel(R) I219-V ADL(17)"),
279 "Intel(R) I219-LM MTP(18)"),
281 "Intel(R) I219-V MTP(18)"),
283 "Intel(R) I219-LM ADL(19)"),
285 "Intel(R) I219-V ADL(19)"),
287 "Intel(R) I219-LM LNL(20)"),
289 "Intel(R) I219-V LNL(20)"),
291 "Intel(R) I219-LM LNL(21)"),
293 "Intel(R) I219-V LNL(21)"),
295 "Intel(R) I219-LM RPL(22)"),
297 "Intel(R) I219-V RPL(22)"),
299 "Intel(R) I219-LM RPL(23)"),
301 "Intel(R) I219-V RPL(23)"),
303 "Intel(R) I219-LM ARL(24)"),
305 "Intel(R) I219-V ARL(24)"),
307 "Intel(R) I219-LM PTP(25)"),
309 "Intel(R) I219-V PTP(25)"),
311 "Intel(R) I219-LM PTP(26)"),
313 "Intel(R) I219-V PTP(26)"),
315 "Intel(R) I219-LM PTP(27)"),
317 "Intel(R) I219-V PTP(27)"),
324 /* Intel(R) - igb-class devices */
354 "Intel(R) I340-T2 82580 (Dual Copper)"),
356 "Intel(R) I340-F4 82580 (Quad Fiber)"),
360 "Intel(R) I347-AT4 DH89XXCC"),
481 /* MSI-X handlers */
650 &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs");
652 &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs");
658 "Default transmit interrupt delay limit in usecs");
661 "Default receive interrupt delay limit in usecs");
677 /* Energy efficient ethernet - default to OFF */
771 struct e1000_hw *hw = &sc->hw;
851 if_softc_ctx_t scctx = sc->shared;
852 struct rx_ring *rxr = &rx_que->rxr;
853 struct tx_ring *txr = &tx_que->txr;
854 int ntxd = scctx->isc_ntxd[0];
855 int nrxd = scctx->isc_nrxd[0];
859 u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
860 u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
863 j, rxr->rx_base[j].read.buffer_addr, staterr, length);
867 unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
872 j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
873 buf->eop != -1 ?
874 txr->tx_base[buf->eop].upper.fields.status &
905 switch (sc->hw.mac.type) {
969 sc->ctx = sc->osdep.ctx = ctx;
970 sc->dev = sc->osdep.dev = dev;
971 scctx = sc->shared = iflib_get_softc_ctx(ctx);
972 sc->media = iflib_get_media(ctx);
973 hw = &sc->hw;
986 sc->enable_aim = em_enable_aim;
988 CTLFLAG_RW, &sc->enable_aim, 0,
1012 if (hw->mac.type >= e1000_i350) {
1036 scctx->isc_tx_nsegments = EM_MAX_SCATTER;
1037 scctx->isc_nrxqsets_max =
1038 scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
1041 scctx->isc_ntxqsets_max);
1043 if (hw->mac.type >= igb_mac_min) {
1044 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
1046 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
1048 scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
1049 scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
1050 scctx->isc_txrx = &igb_txrx;
1051 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
1052 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
1053 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
1054 scctx->isc_capabilities = scctx->isc_capenable = IGB_CAPS;
1055 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_TSO |
1057 if (hw->mac.type != e1000_82575)
1058 scctx->isc_tx_csum_flags |= CSUM_SCTP | CSUM_IP6_SCTP;
1064 scctx->isc_msix_bar = pci_msix_table_bar(dev);
1065 } else if (hw->mac.type >= em_mac_min) {
1066 scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
1068 scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
1070 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
1071 scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
1072 scctx->isc_txrx = &em_txrx;
1073 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
1074 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
1075 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
1076 scctx->isc_capabilities = scctx->isc_capenable = EM_CAPS;
1077 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
1081 scctx->isc_capenable &= ~IFCAP_TSO;
1086 * i218-i219 Specification Update 1.5.4.5
1088 if (hw->mac.type == e1000_pch_spt)
1089 scctx->isc_capenable &= ~IFCAP_TSO;
1092 * We support MSI-X with 82574 only, but indicate to iflib(4)
1095 if (hw->mac.type == e1000_82574) {
1096 scctx->isc_msix_bar = pci_msix_table_bar(dev);
1098 scctx->isc_msix_bar = -1;
1099 scctx->isc_disable_msix = 1;
1102 scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) *
1104 scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) *
1106 scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
1107 scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
1108 scctx->isc_txrx = &lem_txrx;
1109 scctx->isc_tx_tso_segments_max = EM_MAX_SCATTER;
1110 scctx->isc_tx_tso_size_max = EM_TSO_SIZE;
1111 scctx->isc_tx_tso_segsize_max = EM_TSO_SEG_SIZE;
1112 scctx->isc_capabilities = scctx->isc_capenable = LEM_CAPS;
1114 scctx->isc_capabilities |= IFCAP_TSO6;
1115 scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
1119 scctx->isc_capenable &= ~IFCAP_TSO;
1122 if (hw->device_id == E1000_DEV_ID_82541ER ||
1123 hw->device_id == E1000_DEV_ID_82541ER_LOM) {
1124 scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING;
1125 scctx->isc_capenable = scctx->isc_capabilities;
1128 if (hw->mac.type == e1000_82542) {
1129 scctx->isc_capabilities &= ~(IFCAP_HWCSUM |
1133 scctx->isc_capenable = scctx->isc_capabilities;
1136 if (hw->mac.type < e1000_82544 ||
1137 hw->mac.type == e1000_82547 ||
1138 hw->mac.type == e1000_82547_rev_2) {
1139 scctx->isc_capabilities &=
1141 scctx->isc_capenable = scctx->isc_capabilities;
1144 if (hw->mac.type < e1000_82545){
1145 scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6;
1146 scctx->isc_capenable = scctx->isc_capabilities;
1149 * "PCI/PCI-X SDM 4.0" page 33 (b):
1152 if (hw->mac.type == e1000_82547 ||
1153 hw->mac.type == e1000_82547_rev_2)
1154 scctx->isc_capenable &= ~(IFCAP_HWCSUM |
1158 scctx->isc_msix_bar = 0;
1174 if ((hw->mac.type == e1000_ich8lan) ||
1175 (hw->mac.type == e1000_ich9lan) ||
1176 (hw->mac.type == e1000_ich10lan) ||
1177 (hw->mac.type == e1000_pchlan) ||
1178 (hw->mac.type == e1000_pch2lan) ||
1179 (hw->mac.type == e1000_pch_lpt)) {
1181 sc->flash = bus_alloc_resource_any(dev,
1183 if (sc->flash == NULL) {
1189 hw->flash_address = (u8 *)sc->flash;
1190 sc->osdep.flash_bus_space_tag =
1191 rman_get_bustag(sc->flash);
1192 sc->osdep.flash_bus_space_handle =
1193 rman_get_bushandle(sc->flash);
1201 else if (hw->mac.type >= e1000_pch_spt) {
1202 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag;
1203 sc->osdep.flash_bus_space_handle =
1204 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR;
1220 if (hw->mac.type < igb_mac_min) {
1222 "receive interrupt delay in usecs", &sc->rx_int_delay,
1225 "transmit interrupt delay in usecs", &sc->tx_int_delay,
1228 if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) {
1230 "receive interrupt delay limit in usecs",
1231 &sc->rx_abs_int_delay,
1234 "transmit interrupt delay limit in usecs",
1235 &sc->tx_abs_int_delay,
1239 hw->mac.autoneg = DO_AUTO_NEG;
1240 hw->phy.autoneg_wait_to_complete = false;
1241 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1243 if (hw->mac.type < em_mac_min) {
1248 if (hw->phy.media_type == e1000_media_type_copper) {
1249 hw->phy.mdix = AUTO_ALL_MODES;
1250 hw->phy.disable_polarity_correction = false;
1251 hw->phy.ms_type = EM_MASTER_SLAVE;
1258 scctx->isc_max_frame_size = hw->mac.max_frame_size =
1265 hw->mac.report_tx_early = 1;
1268 sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
1270 if (sc->mta == NULL) {
1278 sc->tso_automasked = 0;
1283 "PHY reset is blocked due to SOL/IDER session.\n");
1286 if (hw->mac.type < igb_mac_min)
1287 hw->dev_spec.ich8lan.eee_disable = eee_setting;
1289 hw->dev_spec._82575.eee_disable = eee_setting;
1304 ** Some PCI-E parts fail the first check due to
1324 if (!em_is_valid_ether_addr(hw->mac.addr)) {
1325 if (sc->vf_ifp) {
1327 (struct ether_addr *)hw->mac.addr);
1341 * Get Wake-on-Lan and Management info for later use
1346 scctx->isc_capenable &= ~IFCAP_WOL;
1347 if (sc->wol != 0)
1348 scctx->isc_capenable |= IFCAP_WOL_MAGIC;
1350 iflib_set_mac(ctx, hw->mac.addr);
1358 free(sc->mta, M_DEVBUF);
1367 struct e1000_hw *hw = &sc->hw;
1373 device_printf(sc->dev, "Interface setup failed: %d\n", error);
1381 hw->mac.get_link_status = 1;
1385 /* Non-AMT based hardware can now take control from firmware */
1386 if (sc->has_manage && !sc->has_amt)
1417 e1000_phy_hw_reset(&sc->hw);
1422 free(sc->mta, M_DEVBUF);
1423 sc->mta = NULL;
1459 if (sc->hw.mac.type == e1000_pch2lan)
1460 e1000_resume_workarounds_pchlan(&sc->hw);
1476 switch (sc->hw.mac.type) {
1504 if (sc->hw.mac.type >= igb_mac_min)
1509 if (mtu > max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
1513 scctx->isc_max_frame_size = sc->hw.mac.max_frame_size =
1531 if_softc_ctx_t scctx = sc->shared;
1539 bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1542 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1550 if (sc->hw.mac.type == e1000_82571) {
1551 e1000_set_laa_state_82571(&sc->hw, true);
1552 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1553 E1000_RAR_ENTRIES - 1);
1560 for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues;
1562 struct tx_ring *txr = &tx_que->txr;
1564 txr->tx_rs_cidx = txr->tx_rs_pidx;
1568 * off-by-one error when calculating how many descriptors are
1571 txr->tx_cidx_processed = scctx->isc_ntxd[0] - 1;
1575 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1578 if (sc->hw.mac.type >= igb_mac_min)
1579 e1000_rx_fifo_flush_base(&sc->hw);
1590 sc->rx_mbuf_sz = iflib_get_rx_mbuf_sz(ctx);
1598 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1600 /* MSI-X configuration for 82574 */
1601 if (sc->hw.mac.type == e1000_82574) {
1602 int tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1605 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1606 /* Set the IVAR - interrupt vector routing. */
1607 E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars);
1608 } else if (sc->intr_type == IFLIB_INTR_MSIX) {
1614 E1000_READ_REG(&sc->hw, E1000_ICR);
1615 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1618 if (sc->has_manage && sc->has_amt)
1622 if (sc->hw.mac.type >= igb_mac_min &&
1623 sc->hw.phy.media_type == e1000_media_type_copper) {
1624 if (sc->hw.mac.type == e1000_i354)
1625 e1000_set_eee_i354(&sc->hw, true, true);
1627 e1000_set_eee_i350(&sc->hw, true, true);
1646 struct e1000_hw *hw = &sc->hw;
1654 if ((txr->tx_bytes == 0) && (rxr->rx_bytes == 0))
1659 if (sc->enable_aim) {
1660 nextlatency = rxr->rx_nextlatency;
1662 /* Use half default (4K) ITR if sub-gig */
1663 if (sc->link_speed != 1000) {
1668 if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) {
1670 sc->enable_aim = 0;
1675 if (txr->tx_bytes && txr->tx_packets) {
1676 bytes = txr->tx_bytes;
1677 bytes_packets = txr->tx_bytes/txr->tx_packets;
1678 packets = txr->tx_packets;
1680 if (rxr->rx_bytes && rxr->rx_packets) {
1681 bytes = max(bytes, rxr->rx_bytes);
1683 max(bytes_packets, rxr->rx_bytes/rxr->rx_packets);
1684 packets = max(packets, rxr->rx_packets);
1724 device_printf(sc->dev,
1730 if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest)
1734 rxr->rx_nextlatency = nextlatency;
1738 rxr->rx_nextlatency = nextlatency;
1759 if (hw->mac.type >= igb_mac_min) {
1762 if (hw->mac.type == e1000_82575)
1767 if (newitr != que->itr_setting) {
1768 que->itr_setting = newitr;
1769 E1000_WRITE_REG(hw, E1000_EITR(que->msix),
1770 que->itr_setting);
1775 if (newitr != que->itr_setting) {
1776 que->itr_setting = newitr;
1777 if (hw->mac.type == e1000_82574 && que->msix) {
1779 E1000_EITR_82574(que->msix),
1780 que->itr_setting);
1783 que->itr_setting);
1791 * Fast Legacy/MSI Combined Interrupt Service routine
1798 struct e1000_hw *hw = &sc->hw;
1799 struct em_rx_queue *que = &sc->rx_queues[0];
1800 struct tx_ring *txr = &sc->tx_queues[0].txr;
1801 struct rx_ring *rxr = &que->rxr;
1802 if_ctx_t ctx = sc->ctx;
1819 if (hw->mac.type >= e1000_82571 &&
1824 * Only MSI-X interrupts have one-shot behavior by taking advantage
1836 sc->rx_overruns++;
1838 if (hw->mac.type >= e1000_82540)
1842 txr->tx_bytes = 0;
1843 txr->tx_packets = 0;
1844 rxr->rx_bytes = 0;
1845 rxr->rx_packets = 0;
1854 struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1856 E1000_WRITE_REG(&sc->hw, E1000_IMS, rxq->eims);
1864 struct em_tx_queue *txq = &sc->tx_queues[txqid];
1866 E1000_WRITE_REG(&sc->hw, E1000_IMS, txq->eims);
1874 struct em_rx_queue *rxq = &sc->rx_queues[rxqid];
1876 E1000_WRITE_REG(&sc->hw, E1000_EIMS, rxq->eims);
1884 struct em_tx_queue *txq = &sc->tx_queues[txqid];
1886 E1000_WRITE_REG(&sc->hw, E1000_EIMS, txq->eims);
1892 * MSI-X RX Interrupt Service routine
1899 struct e1000_softc *sc = que->sc;
1900 struct tx_ring *txr = &sc->tx_queues[que->msix].txr;
1901 struct rx_ring *rxr = &que->rxr;
1903 ++que->irqs;
1908 txr->tx_bytes = 0;
1909 txr->tx_packets = 0;
1910 rxr->rx_bytes = 0;
1911 rxr->rx_packets = 0;
1918 * MSI-X Link Fast Interrupt Service routine
1927 ++sc->link_irq;
1928 MPASS(sc->hw.back != NULL);
1929 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1932 sc->rx_overruns++;
1935 em_handle_link(sc->ctx);
1937 /* Re-arm unconditionally */
1938 if (sc->hw.mac.type >= igb_mac_min) {
1939 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1940 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
1941 } else if (sc->hw.mac.type == e1000_82574) {
1942 E1000_WRITE_REG(&sc->hw, E1000_IMS,
1950 E1000_WRITE_REG(&sc->hw, E1000_ICS, sc->ims);
1952 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
1963 sc->hw.mac.get_link_status = 1;
1985 ifmr->ifm_status = IFM_AVALID;
1986 ifmr->ifm_active = IFM_ETHER;
1988 if (!sc->link_active) {
1992 ifmr->ifm_status |= IFM_ACTIVE;
1994 if ((sc->hw.phy.media_type == e1000_media_type_fiber) ||
1995 (sc->hw.phy.media_type == e1000_media_type_internal_serdes)) {
1996 if (sc->hw.mac.type == e1000_82545)
1998 switch (sc->link_speed) {
2000 ifmr->ifm_active |= IFM_10_FL;
2003 ifmr->ifm_active |= IFM_100_FX;
2007 ifmr->ifm_active |= fiber_type | IFM_FDX;
2011 switch (sc->link_speed) {
2013 ifmr->ifm_active |= IFM_10_T;
2016 ifmr->ifm_active |= IFM_100_TX;
2019 ifmr->ifm_active |= IFM_1000_T;
2024 if (sc->link_duplex == FULL_DUPLEX)
2025 ifmr->ifm_active |= IFM_FDX;
2027 ifmr->ifm_active |= IFM_HDX;
2046 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2049 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2051 sc->hw.mac.autoneg = DO_AUTO_NEG;
2052 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
2057 sc->hw.mac.autoneg = DO_AUTO_NEG;
2058 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
2061 sc->hw.mac.autoneg = DO_AUTO_NEG;
2062 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2063 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL;
2064 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
2066 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF;
2067 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
2071 sc->hw.mac.autoneg = DO_AUTO_NEG;
2072 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2073 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL;
2074 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
2076 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF;
2077 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
2081 sc->hw.mac.autoneg = false;
2082 sc->hw.phy.autoneg_advertised = 0;
2083 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
2084 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
2086 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
2089 sc->hw.mac.autoneg = false;
2090 sc->hw.phy.autoneg_advertised = 0;
2091 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
2092 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
2094 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
2097 device_printf(sc->dev, "Unsupported media type\n");
2113 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2123 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2131 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2136 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2174 mta = sc->mta;
2177 if (sc->hw.mac.type == e1000_82542 &&
2178 sc->hw.revision_id == E1000_REVISION_2) {
2179 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2180 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2181 e1000_pci_clear_mwi(&sc->hw);
2183 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2190 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
2192 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2203 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2205 if (sc->hw.mac.type == e1000_82542 &&
2206 sc->hw.revision_id == E1000_REVISION_2) {
2207 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2209 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
2211 if (sc->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
2212 e1000_pci_set_mwi(&sc->hw);
2221 * controller-specific hardware patting.
2237 struct e1000_hw *hw = &sc->hw;
2243 /* Get the cached link value or read phy for real */
2244 switch (hw->phy.media_type) {
2246 if (hw->mac.get_link_status) {
2247 if (hw->mac.type == e1000_pch_spt)
2249 /* Do the work to read phy */
2251 link_check = !hw->mac.get_link_status;
2265 link_check = hw->mac.serdes_has_link;
2270 link_check = !hw->mac.get_link_status;
2277 if (hw->mac.type == e1000_i350) {
2283 if (link_check && (sc->link_active == 0)) {
2284 e1000_get_speed_and_duplex(hw, &sc->link_speed,
2285 &sc->link_duplex);
2286 /* Check if we must disable SPEED_MODE bit on PCI-E */
2287 if ((sc->link_speed != SPEED_1000) &&
2288 ((hw->mac.type == e1000_82571) ||
2289 (hw->mac.type == e1000_82572))) {
2297 sc->link_speed,
2298 ((sc->link_duplex == FULL_DUPLEX) ?
2300 sc->link_active = 1;
2301 sc->smartspeed = 0;
2306 /* Delay Link Up for Phy update */
2307 if (((hw->mac.type == e1000_i210) ||
2308 (hw->mac.type == e1000_i211)) &&
2309 (hw->phy.id == I210_I_PHY_ID))
2312 if (hw->dev_spec._82575.media_changed &&
2313 hw->mac.type >= igb_mac_min) {
2314 hw->dev_spec._82575.media_changed = false;
2315 sc->flags |= IGB_MEDIA_RESET;
2319 if (hw->mac.type < igb_mac_min)
2325 IF_Mbps(sc->link_speed));
2326 } else if (!link_check && (sc->link_active == 1)) {
2327 sc->link_speed = 0;
2328 sc->link_duplex = 0;
2329 sc->link_active = 0;
2335 if (hw->mac.type == e1000_82571 && e1000_get_laa_state_82571(hw))
2336 e1000_rar_set(hw, hw->mac.addr, 0);
2338 if (hw->mac.type < em_mac_min)
2351 sc->watchdog_events++;
2368 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min)
2371 e1000_reset_hw(&sc->hw);
2372 if (sc->hw.mac.type >= e1000_82544)
2373 E1000_WRITE_REG(&sc->hw, E1000_WUFC, 0);
2375 e1000_led_off(&sc->hw);
2376 e1000_cleanup_led(&sc->hw);
2391 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
2394 sc->hw.vendor_id = pci_get_vendor(dev);
2395 sc->hw.device_id = pci_get_device(dev);
2396 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
2397 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
2398 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
2401 if (e1000_set_mac_type(&sc->hw)) {
2407 if ((sc->hw.mac.type == e1000_vfadapt) ||
2408 (sc->hw.mac.type == e1000_vfadapt_i350))
2409 sc->vf_ifp = 1;
2411 sc->vf_ifp = 0;
2422 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2424 if (sc->memory == NULL) {
2429 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
2430 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
2431 sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
2434 if (sc->hw.mac.type < em_mac_min && sc->hw.mac.type > e1000_82543) {
2450 sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2452 if (sc->ioport == NULL) {
2457 sc->hw.io_base = 0;
2458 sc->osdep.io_bus_space_tag =
2459 rman_get_bustag(sc->ioport);
2460 sc->osdep.io_bus_space_handle =
2461 rman_get_bushandle(sc->ioport);
2464 sc->hw.back = &sc->osdep;
2471 * Set up the MSI-X Interrupt handlers
2478 struct em_rx_queue *rx_que = sc->rx_queues;
2479 struct em_tx_queue *tx_que = sc->tx_queues;
2484 for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
2487 error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid,
2488 IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
2493 sc->rx_num_queues = i + 1;
2497 rx_que->msix = vector;
2501 * in E1000_IMS -- bits 20 and 21
2503 * NOTHING to do with the MSI-X vector
2505 if (sc->hw.mac.type == e1000_82574) {
2506 rx_que->eims = 1 << (20 + i);
2507 sc->ims |= rx_que->eims;
2508 sc->ivars |= (8 | rx_que->msix) << (i * 4);
2509 } else if (sc->hw.mac.type == e1000_82575)
2510 rx_que->eims = E1000_EICR_TX_QUEUE0 << vector;
2512 rx_que->eims = 1 << vector;
2517 for (i = 0; i < sc->tx_num_queues; i++, tx_que++, vector++) {
2519 tx_que = &sc->tx_queues[i];
2521 &sc->rx_queues[i % sc->rx_num_queues].que_irq,
2522 IFLIB_INTR_TX, tx_que, tx_que->me, buf);
2524 tx_que->msix = (vector % sc->rx_num_queues);
2528 * in E1000_IMS -- bits 22 and 23
2530 * NOTHING to do with the MSI-X vector
2532 if (sc->hw.mac.type == e1000_82574) {
2533 tx_que->eims = 1 << (22 + i);
2534 sc->ims |= tx_que->eims;
2535 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4));
2536 } else if (sc->hw.mac.type == e1000_82575) {
2537 tx_que->eims = E1000_EICR_TX_QUEUE0 << i;
2539 tx_que->eims = 1 << i;
2545 error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN,
2553 sc->linkvec = rx_vectors;
2554 if (sc->hw.mac.type < igb_mac_min) {
2555 sc->ivars |= (8 | rx_vectors) << 16;
2556 sc->ivars |= 0x80000000;
2558 sc->ims |= E1000_IMS_OTHER;
2563 iflib_irq_free(ctx, &sc->irq);
2564 rx_que = sc->rx_queues;
2565 for (int i = 0; i < sc->rx_num_queues; i++, rx_que++)
2566 iflib_irq_free(ctx, &rx_que->que_irq);
2573 struct e1000_hw *hw = &sc->hw;
2579 if (hw->mac.type != e1000_82575)
2584 /* Turn on MSI-X */
2585 switch (hw->mac.type) {
2594 for (int i = 0; i < sc->rx_num_queues; i++) {
2597 rx_que = &sc->rx_queues[i];
2600 ivar |= (rx_que->msix | E1000_IVAR_VALID) <<
2604 ivar |= rx_que->msix | E1000_IVAR_VALID;
2609 for (int i = 0; i < sc->tx_num_queues; i++) {
2612 tx_que = &sc->tx_queues[i];
2615 ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
2619 ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
2623 sc->que_mask |= tx_que->eims;
2627 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2628 sc->link_mask = 1 << sc->linkvec;
2633 for (int i = 0; i < sc->rx_num_queues; i++) {
2636 rx_que = &sc->rx_queues[i];
2639 ivar |= rx_que->msix | E1000_IVAR_VALID;
2642 ivar |= (rx_que->msix | E1000_IVAR_VALID) <<
2646 sc->que_mask |= rx_que->eims;
2649 for (int i = 0; i < sc->tx_num_queues; i++) {
2652 tx_que = &sc->tx_queues[i];
2655 ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
2659 ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
2663 sc->que_mask |= tx_que->eims;
2667 ivar = (sc->linkvec | E1000_IVAR_VALID) << 8;
2668 sc->link_mask = 1 << sc->linkvec;
2673 /* enable MSI-X support*/
2676 /* Auto-Mask interrupts upon ICR read. */
2682 for (int i = 0; i < sc->rx_num_queues; i++) {
2683 rx_que = &sc->rx_queues[i];
2686 rx_que->eims = tmp;
2688 rx_que->eims);
2689 sc->que_mask |= rx_que->eims;
2693 E1000_WRITE_REG(hw, E1000_MSIXBM(sc->linkvec),
2695 sc->link_mask |= E1000_EIMS_OTHER;
2704 if (hw->mac.type == e1000_82575)
2709 for (int i = 0; i < sc->rx_num_queues; i++) {
2710 rx_que = &sc->rx_queues[i];
2711 E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
2722 struct em_rx_queue *que = sc->rx_queues;
2725 /* Release all MSI-X queue resources */
2726 if (sc->intr_type == IFLIB_INTR_MSIX)
2727 iflib_irq_free(ctx, &sc->irq);
2730 for (int i = 0; i < sc->rx_num_queues; i++, que++) {
2731 iflib_irq_free(ctx, &que->que_irq);
2735 if (sc->memory != NULL) {
2737 rman_get_rid(sc->memory), sc->memory);
2738 sc->memory = NULL;
2741 if (sc->flash != NULL) {
2743 rman_get_rid(sc->flash), sc->flash);
2744 sc->flash = NULL;
2747 if (sc->ioport != NULL) {
2749 rman_get_rid(sc->ioport), sc->ioport);
2750 sc->ioport = NULL;
2754 /* Set up MSI or MSI-X */
2760 if (sc->hw.mac.type == e1000_82574) {
2776 if (sc->link_active || (sc->hw.phy.type != e1000_phy_igp) ||
2777 sc->hw.mac.autoneg == 0 ||
2778 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2781 if (sc->smartspeed == 0) {
2783 * we assume back-to-back */
2784 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2787 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2789 e1000_read_phy_reg(&sc->hw,
2793 e1000_write_phy_reg(&sc->hw,
2795 sc->smartspeed++;
2796 if(sc->hw.mac.autoneg &&
2797 !e1000_copper_link_autoneg(&sc->hw) &&
2798 !e1000_read_phy_reg(&sc->hw,
2802 e1000_write_phy_reg(&sc->hw,
2808 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2810 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2812 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2813 if(sc->hw.mac.autoneg &&
2814 !e1000_copper_link_autoneg(&sc->hw) &&
2815 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2818 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2822 if(sc->smartspeed++ == EM_SMARTSPEED_MAX)
2823 sc->smartspeed = 0;
2834 device_t dev = sc->dev;
2835 struct e1000_hw *hw = &sc->hw;
2840 if (hw->mac.type == e1000_i211)
2843 max_frame_size = sc->shared->isc_max_frame_size;
2844 if (hw->mac.type > e1000_82580) {
2846 if (sc->dmac == 0) { /* Disabling it */
2855 hwm = 64 * pba - max_frame_size / 16;
2856 if (hwm < 64 * (pba - 6))
2857 hwm = 64 * (pba - 6);
2865 dmac = pba - max_frame_size / 512;
2866 if (dmac < pba - 10)
2867 dmac = pba - 10;
2882 if (hw->mac.type == e1000_i354) {
2886 reg |= ((sc->dmac * 5) >> 6);
2888 reg |= (sc->dmac >> 5);
2890 reg |= (sc->dmac >> 5);
2899 if (hw->mac.type == e1000_i350)
2903 ** which is 0x4*2 = 0xA. But delay is still 4 usec
2905 if (hw->mac.type == e1000_i354) {
2919 E1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_TXPBSIZE -
2927 } else if (hw->mac.type == e1000_82580) {
2938 * em_flush_tx_ring - remove all descriptors from the tx_ring
2948 struct e1000_hw *hw = &sc->hw;
2949 struct tx_ring *txr = &sc->tx_queues->txr;
2957 txd = &txr->tx_base[txr->tx_cidx_processed];
2960 txd->buffer_addr = txr->tx_paddr;
2961 txd->lower.data = htole32(txd_lower | size);
2962 txd->upper.data = 0;
2967 E1000_WRITE_REG(hw, E1000_TDT(0), txr->tx_cidx_processed);
2973 * em_flush_rx_ring - remove all descriptors from the rx_ring
2980 struct e1000_hw *hw = &sc->hw;
3007 * em_flush_desc_rings - remove all descriptors from the descriptor rings
3019 struct e1000_hw *hw = &sc->hw;
3020 device_t dev = sc->dev;
3055 struct e1000_hw *hw = &sc->hw;
3064 if (!em_smart_pwr_down && (hw->mac.type == e1000_82571 ||
3065 hw->mac.type == e1000_82572)) {
3079 switch (hw->mac.type) {
3083 if (hw->mac.max_frame_size > 8192)
3108 if (hw->mac.max_frame_size > 4096)
3145 if (hw->mac.max_frame_size > 8192)
3152 if ((hw->mac.type == e1000_82575) && (if_getmtu(ifp) > ETHERMTU)) {
3157 min_tx = (hw->mac.max_frame_size +
3158 sizeof(struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2;
3161 min_rx = hw->mac.max_frame_size;
3165 ((min_tx - tx_space) < pba)) {
3166 pba = pba - (min_tx - tx_space);
3177 if (hw->mac.type < igb_mac_min)
3185 * - High water mark should allow for at least two frames to be
3187 * - Low water mark works best when it is very near the high water
3195 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
3198 hw->fc.high_water = rx_buffer_size -
3199 roundup2(hw->mac.max_frame_size, 1024);
3200 hw->fc.low_water = hw->fc.high_water - 1500;
3202 if (sc->fc) /* locally set flow control value? */
3203 hw->fc.requested_mode = sc->fc;
3205 hw->fc.requested_mode = e1000_fc_full;
3207 if (hw->mac.type == e1000_80003es2lan)
3208 hw->fc.pause_time = 0xFFFF;
3210 hw->fc.pause_time = EM_FC_PAUSE_TIME;
3212 hw->fc.send_xon = true;
3215 switch (hw->mac.type) {
3218 hw->fc.requested_mode = e1000_fc_rx_pause;
3219 hw->fc.pause_time = 0xFFFF; /* override */
3221 hw->fc.high_water = 0x3500;
3222 hw->fc.low_water = 0x1500;
3224 hw->fc.high_water = 0x5000;
3225 hw->fc.low_water = 0x3000;
3227 hw->fc.refresh_time = 0x1000;
3237 hw->fc.high_water = 0x5C20;
3238 hw->fc.low_water = 0x5048;
3239 hw->fc.pause_time = 0x0650;
3240 hw->fc.refresh_time = 0x0400;
3249 /* 8-byte granularity */
3250 hw->fc.low_water = hw->fc.high_water - 8;
3259 /* 16-byte granularity */
3260 hw->fc.low_water = hw->fc.high_water - 16;
3265 hw->fc.high_water = 0x2800;
3266 hw->fc.low_water = hw->fc.high_water - 8;
3271 if (hw->mac.type == e1000_80003es2lan)
3272 hw->fc.pause_time = 0xFFFF;
3277 if (sc->hw.mac.type >= e1000_pch_spt && sc->hw.mac.type < igb_mac_min)
3282 if (hw->mac.type >= igb_mac_min) {
3288 if (sc->flags & IGB_MEDIA_RESET) {
3291 sc->flags &= ~IGB_MEDIA_RESET;
3293 /* and a re-init */
3298 if (hw->mac.type >= igb_mac_min)
3302 sc->pba = pba;
3320 struct e1000_hw *hw = &sc->hw;
3341 q = (i % sc->rx_num_queues) << 7;
3359 struct e1000_hw *hw = &sc->hw;
3366 if (hw->mac.type == e1000_82575)
3375 * This just allocates buckets to queues using round-robin
3400 queue_id = queue_id % sc->rx_num_queues;
3402 queue_id = (i % sc->rx_num_queues);
3461 if_softc_ctx_t scctx = sc->shared;
3466 if (sc->tx_num_queues == 1) {
3467 if_setsendqlen(ifp, scctx->isc_ntxd[0] - 1);
3475 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
3476 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
3479 if (sc->hw.mac.type == e1000_82545)
3481 ifmedia_add(sc->media,
3483 ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL);
3485 ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
3486 ifmedia_add(sc->media,
3488 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
3489 ifmedia_add(sc->media,
3491 if (sc->hw.phy.type != e1000_phy_ife) {
3492 ifmedia_add(sc->media,
3494 ifmedia_add(sc->media,
3498 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3499 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
3508 if_softc_ctx_t scctx = sc->shared;
3513 MPASS(sc->tx_num_queues > 0);
3514 MPASS(sc->tx_num_queues == ntxqsets);
3517 if (!(sc->tx_queues =
3519 sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
3525 for (i = 0, que = sc->tx_queues; i < sc->tx_num_queues; i++, que++) {
3528 struct tx_ring *txr = &que->txr;
3529 txr->sc = que->sc = sc;
3530 que->me = txr->me = i;
3533 if (!(txr->tx_rsq =
3534 (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0],
3541 for (j = 0; j < scctx->isc_ntxd[0]; j++)
3542 txr->tx_rsq[j] = QIDX_INVALID;
3544 txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
3545 txr->tx_paddr = paddrs[i*ntxqs];
3550 "allocated for %d tx_queues\n", sc->tx_num_queues);
3566 MPASS(sc->rx_num_queues > 0);
3567 MPASS(sc->rx_num_queues == nrxqsets);
3570 if (!(sc->rx_queues =
3572 sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
3579 for (i = 0, que = sc->rx_queues; i < nrxqsets; i++, que++) {
3581 struct rx_ring *rxr = &que->rxr;
3582 rxr->sc = que->sc = sc;
3583 rxr->que = que;
3584 que->me = rxr->me = i;
3587 rxr->rx_base =
3589 rxr->rx_paddr = paddrs[i*nrxqs];
3594 "allocated for %d rx_queues\n", sc->rx_num_queues);
3606 struct em_tx_queue *tx_que = sc->tx_queues;
3607 struct em_rx_queue *rx_que = sc->rx_queues;
3610 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
3611 struct tx_ring *txr = &tx_que->txr;
3612 if (txr->tx_rsq == NULL)
3615 free(txr->tx_rsq, M_DEVBUF);
3616 txr->tx_rsq = NULL;
3618 free(sc->tx_queues, M_DEVBUF);
3619 sc->tx_queues = NULL;
3623 free(sc->rx_queues, M_DEVBUF);
3624 sc->rx_queues = NULL;
3637 if_softc_ctx_t scctx = sc->shared;
3640 struct e1000_hw *hw = &sc->hw;
3645 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
3649 que = &sc->tx_queues[i];
3650 txr = &que->txr;
3651 bus_addr = txr->tx_paddr;
3654 offp = (caddr_t)&txr->csum_flags;
3656 bzero(offp, endp - offp);
3660 scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
3683 switch (hw->mac.type) {
3695 if (hw->phy.media_type == e1000_media_type_fiber ||
3696 hw->phy.media_type == e1000_media_type_internal_serdes)
3704 if (hw->mac.type < igb_mac_min) {
3706 E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value);
3708 if (sc->tx_int_delay.value > 0)
3709 sc->txd_cmd |= E1000_TXD_CMD_IDE;
3712 if (hw->mac.type >= e1000_82540)
3713 E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value);
3715 if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
3719 } else if (hw->mac.type == e1000_80003es2lan) {
3727 } else if (hw->mac.type == e1000_82574) {
3730 if ( sc->tx_num_queues > 1) {
3744 if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min)
3751 if (hw->mac.type == e1000_pch_spt) {
3756 /* i218-i219 Specification Update 1.5.4.5 */
3769 #define BSIZEPKT_ROUNDUP ((1<<E1000_SRRCTL_BSIZEPKT_SHIFT)-1)
3775 if_softc_ctx_t scctx = sc->shared;
3777 struct e1000_hw *hw = &sc->hw;
3790 if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
3797 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3813 if (hw->mac.type < igb_mac_min) {
3814 if (hw->mac.type >= e1000_82540) {
3816 sc->rx_abs_int_delay.value);
3829 if (hw->mac.type == e1000_82573)
3833 sc->rx_int_delay.value);
3836 if (hw->mac.type >= em_mac_min) {
3843 * When using MSI-X interrupts we need to throttle
3846 if (hw->mac.type == e1000_82574) {
3860 if (hw->mac.type > e1000_82575)
3862 else if (hw->mac.type < em_mac_min &&
3867 if (hw->mac.type > e1000_82575)
3869 else if (hw->mac.type < em_mac_min)
3873 if (sc->rx_num_queues > 1) {
3877 if (hw->mac.type >= igb_mac_min)
3884 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
3885 struct rx_ring *rxr = &que->rxr;
3887 u64 bus_addr = rxr->rx_paddr;
3889 u32 rdt = sc->rx_num_queues -1; /* default */
3893 scctx->isc_nrxd[0] *
3909 if ((hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_pch2lan ||
3910 hw->mac.type == e1000_ich10lan) && if_getmtu(ifp) > ETHERMTU) {
3913 } else if (hw->mac.type == e1000_82574) {
3914 for (int i = 0; i < sc->rx_num_queues; i++) {
3922 } else if (hw->mac.type >= igb_mac_min) {
3926 psize = scctx->isc_max_frame_size;
3931 if (sc->vf_ifp)
3938 srrctl |= (sc->rx_mbuf_sz + BSIZEPKT_ROUNDUP) >>
3948 if ((sc->rx_num_queues > 1) &&
3949 (sc->fc == e1000_fc_none ||
3950 sc->fc == e1000_fc_rx_pause)) {
3954 for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues;
3956 struct rx_ring *rxr = &que->rxr;
3957 u64 bus_addr = rxr->rx_paddr;
3961 /* Configure for header split? -- ignore for now */
3962 rxr->hdr_split = igb_header_split;
3968 scctx->isc_nrxd[0] *
3984 } else if (hw->mac.type >= e1000_pch2lan) {
3995 if (hw->mac.type < igb_mac_min) {
3996 if (sc->rx_mbuf_sz > 2048 && sc->rx_mbuf_sz <= 4096)
3998 else if (sc->rx_mbuf_sz > 4096 && sc->rx_mbuf_sz <= 8192)
4000 else if (sc->rx_mbuf_sz > 8192)
4032 sc->shadow_vfta[index] |= (1 << bit);
4033 ++sc->num_vlans;
4045 sc->shadow_vfta[index] &= ~(1 << bit);
4046 --sc->num_vlans;
4071 if (sc->shadow_vfta[i] != 0)
4080 struct e1000_hw *hw = &sc->hw;
4092 struct e1000_hw *hw = &sc->hw;
4103 struct e1000_hw *hw = &sc->hw;
4105 if (sc->vf_ifp)
4109 if (hw->mac.type < em_mac_min)
4110 em_if_intr_disable(sc->ctx);
4113 if (sc->shadow_vfta[i] != 0) {
4115 if (sc->vf_ifp)
4116 e1000_vfta_set_vf(hw, sc->shadow_vfta[i],
4119 e1000_write_vfta(hw, i, sc->shadow_vfta[i]);
4122 /* Re-enable interrupts for lem-class devices */
4123 if (hw->mac.type < em_mac_min)
4124 em_if_intr_enable(sc->ctx);
4131 struct e1000_hw *hw = &sc->hw;
4138 if (sc->vf_ifp)
4174 struct e1000_hw *hw = &sc->hw;
4177 if (sc->intr_type == IFLIB_INTR_MSIX) {
4178 E1000_WRITE_REG(hw, EM_EIAC, sc->ims);
4179 ims_mask |= sc->ims;
4190 struct e1000_hw *hw = &sc->hw;
4192 if (sc->intr_type == IFLIB_INTR_MSIX)
4202 struct e1000_hw *hw = &sc->hw;
4205 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
4206 mask = (sc->que_mask | sc->link_mask);
4220 struct e1000_hw *hw = &sc->hw;
4222 if (__predict_true(sc->intr_type == IFLIB_INTR_MSIX)) {
4240 if (sc->has_manage) {
4241 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
4242 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
4253 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
4254 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
4265 if (sc->has_manage) {
4266 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
4268 /* re-enable hardware interception of ARP */
4272 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
4287 if (sc->vf_ifp)
4290 if (sc->hw.mac.type == e1000_82573) {
4291 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
4292 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
4297 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
4298 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
4313 if (!sc->has_manage)
4316 if (sc->hw.mac.type == e1000_82573) {
4317 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
4318 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
4323 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
4324 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
4348 if (!em_unsupported_tso && sc->link_speed &&
4349 sc->link_speed != SPEED_1000 &&
4350 scctx->isc_capenable & IFCAP_TSO) {
4351 device_printf(sc->dev,
4353 sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO;
4354 scctx->isc_capenable &= ~IFCAP_TSO;
4359 } else if (sc->link_speed == SPEED_1000 && sc->tso_automasked) {
4360 device_printf(sc->dev, "Re-enabling TSO for GbE.\n");
4361 scctx->isc_capenable |= sc->tso_automasked;
4362 if_setcapenablebit(ifp, sc->tso_automasked, 0);
4363 sc->tso_automasked = 0;
4374 ** to both system management and wake-on-lan for
4384 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
4387 switch (sc->hw.mac.type) {
4392 e1000_read_nvm(&sc->hw,
4398 if (sc->hw.bus.func == 1) {
4399 e1000_read_nvm(&sc->hw,
4403 e1000_read_nvm(&sc->hw,
4408 sc->has_amt = true;
4413 if (sc->hw.bus.func == 1) {
4414 e1000_read_nvm(&sc->hw,
4418 e1000_read_nvm(&sc->hw,
4438 sc->has_amt = true;
4439 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC);
4442 e1000_read_nvm(&sc->hw,
4447 sc->wol = (E1000_WUFC_MAG | E1000_WUFC_MC);
4456 sc->wol = 0;
4462 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
4464 sc->wol = 0;
4469 sc->wol = 0;
4477 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
4479 sc->wol = 0;
4486 sc->wol = 0;
4517 sc->wol &= ~E1000_WUFC_MAG;
4520 sc->wol &= ~E1000_WUFC_EX;
4523 sc->wol &= ~E1000_WUFC_MC;
4525 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
4527 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
4530 if (!(sc->wol & (E1000_WUFC_EX | E1000_WUFC_MAG | E1000_WUFC_MC)))
4534 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
4536 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
4539 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
4540 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
4541 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
4543 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, ctrl_ext);
4546 if ((sc->hw.mac.type == e1000_ich8lan) ||
4547 (sc->hw.mac.type == e1000_pchlan) ||
4548 (sc->hw.mac.type == e1000_ich9lan) ||
4549 (sc->hw.mac.type == e1000_ich10lan))
4550 e1000_suspend_workarounds_ich8lan(&sc->hw);
4552 if ( sc->hw.mac.type >= e1000_pchlan) {
4558 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
4559 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
4562 if (sc->hw.phy.type == e1000_phy_igp_3)
4563 e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw);
4577 * require thing to be copied into the phy
4582 struct e1000_hw *hw = &sc->hw;
4586 /* copy MAC RARs to PHY RARs */
4589 /* copy MAC MTA to PHY MTA */
4590 for (int i = 0; i < hw->mac.mta_reg_count; i++) {
4597 /* configure PHY Rx Control register */
4617 /* enable PHY wakeup in MAC register */
4620 E1000_WRITE_REG(hw, E1000_WUFC, sc->wol);
4622 /* configure and enable PHY wakeup in PHY registers */
4623 e1000_write_phy_reg(hw, BM_WUFC, sc->wol);
4626 /* activate PHY wakeup */
4627 ret = hw->phy.ops.acquire(hw);
4629 printf("Could not acquire PHY\n");
4636 printf("Could not read PHY page 769\n");
4642 printf("Could not set PHY Host Wakeup bit\n");
4644 hw->phy.ops.release(hw);
4655 e1000_setup_led(&sc->hw);
4656 e1000_led_on(&sc->hw);
4658 e1000_led_off(&sc->hw);
4659 e1000_cleanup_led(&sc->hw);
4671 device_t dev = sc->dev;
4673 switch (sc->hw.mac.type) {
4702 u64 prev_xoffrxc = sc->stats.xoffrxc;
4704 if(sc->hw.phy.media_type == e1000_media_type_copper ||
4705 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
4706 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
4707 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
4709 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
4710 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
4711 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
4712 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
4714 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
4715 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
4716 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
4717 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
4718 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
4719 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
4720 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
4721 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
4726 if (sc->stats.xoffrxc != prev_xoffrxc)
4727 sc->shared->isc_pause_frames = 1;
4728 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
4729 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
4730 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
4731 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
4732 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
4733 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
4734 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
4735 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
4736 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
4737 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
4738 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
4739 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
4741 /* For the 64-bit byte counters the low dword must be read first. */
4744 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCL) +
4745 ((u64)E1000_READ_REG(&sc->hw, E1000_GORCH) << 32);
4746 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCL) +
4747 ((u64)E1000_READ_REG(&sc->hw, E1000_GOTCH) << 32);
4749 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
4750 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
4751 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
4752 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
4753 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
4755 sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC);
4756 sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC);
4757 sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC);
4759 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
4760 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
4762 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
4763 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
4764 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
4765 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
4766 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
4767 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
4768 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
4769 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
4770 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
4771 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
4775 sc->stats.iac += E1000_READ_REG(&sc->hw, E1000_IAC);
4776 sc->stats.icrxptc += E1000_READ_REG(&sc->hw, E1000_ICRXPTC);
4777 sc->stats.icrxatc += E1000_READ_REG(&sc->hw, E1000_ICRXATC);
4778 sc->stats.ictxptc += E1000_READ_REG(&sc->hw, E1000_ICTXPTC);
4779 sc->stats.ictxatc += E1000_READ_REG(&sc->hw, E1000_ICTXATC);
4780 sc->stats.ictxqec += E1000_READ_REG(&sc->hw, E1000_ICTXQEC);
4781 sc->stats.ictxqmtc += E1000_READ_REG(&sc->hw, E1000_ICTXQMTC);
4782 sc->stats.icrxdmtc += E1000_READ_REG(&sc->hw, E1000_ICRXDMTC);
4783 sc->stats.icrxoc += E1000_READ_REG(&sc->hw, E1000_ICRXOC);
4785 if (sc->hw.mac.type >= e1000_82543) {
4786 sc->stats.algnerrc +=
4787 E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
4788 sc->stats.rxerrc +=
4789 E1000_READ_REG(&sc->hw, E1000_RXERRC);
4790 sc->stats.tncrs +=
4791 E1000_READ_REG(&sc->hw, E1000_TNCRS);
4792 sc->stats.cexterr +=
4793 E1000_READ_REG(&sc->hw, E1000_CEXTERR);
4794 sc->stats.tsctc +=
4795 E1000_READ_REG(&sc->hw, E1000_TSCTC);
4796 sc->stats.tsctfc +=
4797 E1000_READ_REG(&sc->hw, E1000_TSCTFC);
4809 return (sc->stats.colc);
4811 return (sc->dropped_pkts + sc->stats.rxerrc +
4812 sc->stats.crcerrs + sc->stats.algnerrc +
4813 sc->stats.ruc + sc->stats.roc +
4814 sc->stats.mpc + sc->stats.cexterr);
4816 return (sc->stats.ecol + sc->stats.latecol +
4817 sc->watchdog_events);
4823 /* em_if_needs_restart - Tell iflib when the driver needs to be reinitialized
4841 /* Export a single 32-bit register via a read-only sysctl. */
4848 sc = oidp->oid_arg1;
4849 val = E1000_READ_REG(&sc->hw, oidp->oid_arg2);
4863 bool tx = oidp->oid_arg2;
4866 tque = oidp->oid_arg1;
4867 hw = &tque->sc->hw;
4868 if (hw->mac.type >= igb_mac_min)
4869 reg = E1000_READ_REG(hw, E1000_EITR(tque->me));
4870 else if (hw->mac.type == e1000_82574 && tque->msix)
4871 reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me));
4875 rque = oidp->oid_arg1;
4876 hw = &rque->sc->hw;
4877 if (hw->mac.type >= igb_mac_min)
4878 reg = E1000_READ_REG(hw, E1000_EITR(rque->msix));
4879 else if (hw->mac.type == e1000_82574 && rque->msix)
4881 E1000_EITR_82574(rque->msix));
4886 if (hw->mac.type < igb_mac_min) {
4900 if (error || !req->newptr)
4911 device_t dev = iflib_get_dev(sc->ctx);
4912 struct em_tx_queue *tx_que = sc->tx_queues;
4913 struct em_rx_queue *rx_que = sc->rx_queues;
4918 struct e1000_hw_stats *stats = &sc->stats;
4928 CTLFLAG_RD, &sc->dropped_pkts,
4931 CTLFLAG_RD, &sc->link_irq,
4932 "Link MSI-X IRQ Handled");
4934 CTLFLAG_RD, &sc->rx_overruns,
4937 CTLFLAG_RD, &sc->watchdog_events,
4948 CTLFLAG_RD, &sc->hw.fc.high_water, 0,
4951 CTLFLAG_RD, &sc->hw.fc.low_water, 0,
4954 for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
4955 struct tx_ring *txr = &tx_que->txr;
4968 E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
4972 E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
4975 CTLFLAG_RD, &txr->tx_irq,
4976 "Queue MSI-X Transmit Interrupts");
4979 for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) {
4980 struct rx_ring *rxr = &rx_que->rxr;
4993 E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
4997 E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
5000 CTLFLAG_RD, &rxr->rx_irq,
5001 "Queue MSI-X Receive Interrupts");
5010 CTLFLAG_RD, &stats->ecol,
5013 CTLFLAG_RD, &stats->scc,
5016 CTLFLAG_RD, &stats->mcc,
5019 CTLFLAG_RD, &stats->latecol,
5022 CTLFLAG_RD, &stats->colc,
5025 CTLFLAG_RD, &sc->stats.symerrs,
5028 CTLFLAG_RD, &sc->stats.sec,
5031 CTLFLAG_RD, &sc->stats.dc,
5034 CTLFLAG_RD, &sc->stats.mpc,
5037 CTLFLAG_RD, &sc->stats.rlec,
5040 CTLFLAG_RD, &sc->stats.rnbc,
5043 CTLFLAG_RD, &sc->stats.ruc,
5046 CTLFLAG_RD, &sc->stats.rfc,
5049 CTLFLAG_RD, &sc->stats.roc,
5052 CTLFLAG_RD, &sc->stats.rjc,
5055 CTLFLAG_RD, &sc->stats.rxerrc,
5058 CTLFLAG_RD, &sc->stats.crcerrs,
5061 CTLFLAG_RD, &sc->stats.algnerrc,
5065 CTLFLAG_RD, &sc->stats.cexterr,
5068 CTLFLAG_RD, &sc->stats.xonrxc,
5071 CTLFLAG_RD, &sc->stats.xontxc,
5074 CTLFLAG_RD, &sc->stats.xoffrxc,
5077 CTLFLAG_RD, &sc->stats.xofftxc,
5080 CTLFLAG_RD, &sc->stats.fcruc,
5083 CTLFLAG_RD, &sc->stats.mgprc,
5086 CTLFLAG_RD, &sc->stats.mgpdc,
5089 CTLFLAG_RD, &sc->stats.mgptc,
5094 CTLFLAG_RD, &sc->stats.tpr,
5097 CTLFLAG_RD, &sc->stats.gprc,
5100 CTLFLAG_RD, &sc->stats.bprc,
5103 CTLFLAG_RD, &sc->stats.mprc,
5106 CTLFLAG_RD, &sc->stats.prc64,
5109 CTLFLAG_RD, &sc->stats.prc127,
5110 "65-127 byte frames received");
5112 CTLFLAG_RD, &sc->stats.prc255,
5113 "128-255 byte frames received");
5115 CTLFLAG_RD, &sc->stats.prc511,
5116 "256-511 byte frames received");
5118 CTLFLAG_RD, &sc->stats.prc1023,
5119 "512-1023 byte frames received");
5121 CTLFLAG_RD, &sc->stats.prc1522,
5122 "1023-1522 byte frames received");
5124 CTLFLAG_RD, &sc->stats.gorc,
5129 CTLFLAG_RD, &sc->stats.gotc,
5132 CTLFLAG_RD, &sc->stats.tpt,
5135 CTLFLAG_RD, &sc->stats.gptc,
5138 CTLFLAG_RD, &sc->stats.bptc,
5141 CTLFLAG_RD, &sc->stats.mptc,
5144 CTLFLAG_RD, &sc->stats.ptc64,
5147 CTLFLAG_RD, &sc->stats.ptc127,
5148 "65-127 byte frames transmitted");
5150 CTLFLAG_RD, &sc->stats.ptc255,
5151 "128-255 byte frames transmitted");
5153 CTLFLAG_RD, &sc->stats.ptc511,
5154 "256-511 byte frames transmitted");
5156 CTLFLAG_RD, &sc->stats.ptc1023,
5157 "512-1023 byte frames transmitted");
5159 CTLFLAG_RD, &sc->stats.ptc1522,
5160 "1024-1522 byte frames transmitted");
5162 CTLFLAG_RD, &sc->stats.tsctc,
5165 CTLFLAG_RD, &sc->stats.tsctfc,
5174 CTLFLAG_RD, &sc->stats.iac,
5178 CTLFLAG_RD, &sc->stats.icrxptc,
5182 CTLFLAG_RD, &sc->stats.icrxatc,
5186 CTLFLAG_RD, &sc->stats.ictxptc,
5190 CTLFLAG_RD, &sc->stats.ictxatc,
5194 CTLFLAG_RD, &sc->stats.ictxqec,
5198 CTLFLAG_RD, &sc->stats.ictxqmtc,
5202 CTLFLAG_RD, &sc->stats.icrxdmtc,
5206 CTLFLAG_RD, &sc->stats.icrxoc,
5214 struct e1000_hw *hw = &sc->hw;
5215 struct e1000_fw_version *fw_ver = &sc->fw_ver;
5227 if (hw->mac.type >= igb_mac_min) {
5242 fw_ver->eep_major = (eep & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT;
5243 fw_ver->eep_minor = (eep & NVM_MINOR_MASK) >> NVM_MINOR_SHIFT;
5244 fw_ver->eep_build = (eep & NVM_IMAGE_ID_MASK);
5253 if (fw_ver->eep_major || fw_ver->eep_minor || fw_ver->eep_build) {
5254 sbuf_printf(buf, "EEPROM V%d.%d-%d", fw_ver->eep_major,
5255 fw_ver->eep_minor, fw_ver->eep_build);
5259 if (fw_ver->invm_major || fw_ver->invm_minor ||
5260 fw_ver->invm_img_type) {
5262 space, fw_ver->invm_major, fw_ver->invm_minor,
5263 fw_ver->invm_img_type);
5267 if (fw_ver->or_valid) {
5268 sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
5269 space, fw_ver->or_major, fw_ver->or_build,
5270 fw_ver->or_patch);
5274 if (fw_ver->etrack_id)
5275 sbuf_printf(buf, "%seTrack 0x%08x", space, fw_ver->etrack_id);
5281 device_t dev = sc->dev;
5291 em_sbuf_fw_version(&sc->fw_ver, buf);
5306 device_t dev = sc->dev;
5316 em_sbuf_fw_version(&sc->fw_ver, buf);
5341 result = -1;
5344 if (error || !req->newptr)
5349 * first 32 16-bit words of the EEPROM to
5361 struct e1000_hw *hw = &sc->hw;
5362 struct sx *iflib_ctx_lock = iflib_ctx_lock_get(sc->ctx);
5394 usecs = info->value;
5396 if (error != 0 || req->newptr == NULL)
5400 info->value = usecs;
5403 sc = info->sc;
5405 regval = E1000_READ_OFFSET(&sc->hw, info->offset);
5408 switch (info->offset) {
5413 sc->txd_cmd &= ~E1000_TXD_CMD_IDE;
5417 sc->txd_cmd |= E1000_TXD_CMD_IDE;
5420 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval);
5431 sc = oidp->oid_arg1;
5432 switch (oidp->oid_arg2) {
5449 val = E1000_READ_REG(&sc->hw, reg);
5452 if (error != 0 || req->newptr == NULL)
5457 E1000_WRITE_REG(&sc->hw, reg, val);
5466 info->sc = sc;
5467 info->offset = offset;
5468 info->value = value;
5469 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
5470 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
5478 * 0 - off
5479 * 1 - rx pause
5480 * 2 - tx pause
5481 * 3 - full
5487 static int input = 3; /* default is full */
5490 error = sysctl_handle_int(oidp, &input, 0, req);
5492 if ((error) || (req->newptr == NULL))
5495 if (input == sc->fc) /* no change? */
5498 switch (input) {
5503 sc->hw.fc.requested_mode = input;
5504 sc->fc = input;
5511 sc->hw.fc.current_mode = sc->hw.fc.requested_mode;
5512 e1000_force_mac_fc(&sc->hw);
5519 * 0/1 - off/on
5521 * 250,500,1000-10000 in thousands
5529 error = sysctl_handle_int(oidp, &sc->dmac, 0, req);
5531 if ((error) || (req->newptr == NULL))
5534 switch (sc->dmac) {
5539 sc->dmac = 1000;
5553 /* Legal values - allow */
5557 sc->dmac = 0;
5561 em_if_init(sc->ctx);
5568 * 0/1 - enabled/disabled
5576 if (sc->hw.mac.type < igb_mac_min)
5577 value = sc->hw.dev_spec.ich8lan.eee_disable;
5579 value = sc->hw.dev_spec._82575.eee_disable;
5581 if (error || req->newptr == NULL)
5583 if (sc->hw.mac.type < igb_mac_min)
5584 sc->hw.dev_spec.ich8lan.eee_disable = (value != 0);
5586 sc->hw.dev_spec._82575.eee_disable = (value != 0);
5587 em_if_init(sc->ctx);
5599 result = -1;
5602 if (error || !req->newptr)
5623 if (error || !req->newptr || result != 1)
5638 * needed for debugging a problem. -jfv
5643 device_t dev = iflib_get_dev(sc->ctx);
5644 if_t ifp = iflib_get_ifp(sc->ctx);
5645 struct tx_ring *txr = &sc->tx_queues->txr;
5646 struct rx_ring *rxr = &sc->rx_queues->rxr;
5658 for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
5659 device_printf(dev, "TX Queue %d ------\n", i);
5661 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
5662 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
5665 for (int j=0; j < sc->rx_num_queues; j++, rxr++) {
5666 device_printf(dev, "RX Queue %d ------\n", j);
5668 E1000_READ_REG(&sc->hw, E1000_RDH(j)),
5669 E1000_READ_REG(&sc->hw, E1000_RDT(j)));
5675 * Write a new value to the EEPROM increasing the number of MSI-X
5682 struct e1000_hw *hw = &sc->hw;
5691 "reported MSI-X vectors from 3 to 5...\n");