Lines Matching +full:phy +full:- +full:input +full:- +full:delay +full:- +full:legacy
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
177 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
262 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
264 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
278 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
280 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
281 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
282 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
288 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
335 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
344 /* Constants used to interpret the masked PCI-X bus speed. */
345 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
346 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
347 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
366 /* 1000/H is not supported, nor spec-compliant. */
403 #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
421 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
728 /* Loop limit on how long we wait for auto-negotiation to complete */
735 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
752 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
764 #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */
923 /* PHY Control Register */
928 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
933 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
938 /* PHY Status Register */
987 /* 1000BASE-T Control Register */
993 /* 1=Configure PHY as Master 0=Configure PHY as Slave */
1003 /* 1000BASE-T Status Register */
1015 /* PHY 1000 MII Register/Bit Definitions */
1016 /* PHY Registers defined by IEEE */
1019 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
1020 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
1026 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1027 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1030 #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */
1047 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1193 /* NVM Commands - Microwire */
1200 /* NVM Commands - SPI */
1204 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1232 /* PCI/PCI-X/PCI-EX Config space */
1256 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1259 /* Bit definitions for valid PHY IDs.
1291 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */
1292 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */
1293 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */
1296 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
1302 /* M88E1000 PHY Specific Control Register */
1307 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1313 /* M88E1000 PHY Specific Status Register */
1318 * 1 = 50-80M
1319 * 2 = 80-110M
1320 * 3 = 110-140M
1346 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */
1347 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */
1350 /* I347AT4 Extended PHY Specific Control Register */
1366 /* I347AT4 PHY Cable Diagnostics Control */
1379 /* BME1000 PHY Specific Control Register */
1383 * 15-5: page
1384 * 4-0: register offset
1392 #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */
1394 #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
1402 /* Page 193 - Port Control Registers */
1407 /* Page 194 - KMRN Registers */
1451 /* Tx Rate-Scheduler Config fields */
1468 /* DMA Coalescing BMC-to-OS Watchdog Enable */