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/freebsd-src/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8195.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gc
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/freebsd-src/sys/contrib/device-tree/Bindings/mfd/
H A Dmediatek,mt8195-scpsys.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/mediatek,mt8195
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/mediatek/
H A Dmediatek,mmsys.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek mmsys controller
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 The MediaTek mmsys system controller provides clock control, routing control,
18 pattern: "^syscon@[0-9a-f]+$"
22 - items:
23 - enum:
24 - mediatek,mt2701-mmsys
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/freebsd-src/sys/contrib/device-tree/Bindings/media/
H A Dmediatek,mt8195-jpegenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
17 const: mediatek,mt8195-jpgenc
19 power-domains:
29 "#address-cells":
32 "#size-cells":
39 "^jpgenc@[0-9a-f]+$":
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H A Dmediatek,mt8195-jpegdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>
17 const: mediatek,mt8195-jpgdec
19 power-domains:
29 "#address-cells":
32 "#size-cells":
39 "^jpgdec@[0-9a-f]+$":
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H A Dmediatek,mdp3-rdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdm
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H A Dmediatek,vcodec-subdev-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 +------------------------------------------------+-------------------------------------+
22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------||-------------------+---------------------||--------------+
26 -------------||-------------||-------------------|---------------------||---------------
27 ||<------------||----------------HW index---------------->|| <child>
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/freebsd-src/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dsc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: mediatek display DSC controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
17 video bit stream. DSC is designed for real-time systems with
18 real-time compression, transmission, decompression and Display.
23 - enum:
24 - mediatek,mt8195-disp-dsc
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H A Dmediatek,dp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Display Port Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Jitao shi <jitao.shi@mediatek.com>
17 In addition, We just need to enable the power domain of DP, so the clock
24 - mediatek,mt8188-dp-tx
25 - mediatek,mt8188-edp-tx
26 - mediatek,mt8195-dp-tx
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H A Dmediatek,merge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15 inputs into one side-by-side output.
24 - enum:
25 - mediatek,mt8173-disp-merge
26 - mediatek,mt8195-disp-merge
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H A Dmediatek,mdp-rdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
15 It provides real time data to the back-end panel driver, such as DSI,
24 const: mediatek,mt8195-vdo1-rdma
32 power-domains:
37 - description: RDMA Clock
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H A Dmediatek,ethdr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
21 These two function blocks read the pre-programmed registers from DRAM and
22 set them to HW in the v-blanking period.
27 - const: mediatek,mt8195-disp-ethdr
28 - items:
29 - const: mediatek,mt8188-disp-ethdr
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H A Dmediatek,aal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dmediatek,color.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dmediatek,ovl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dmediatek,split.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dmediatek,rdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - mediatek,mt8188-disp-padding
25 - mediatek,mt8195-mdp3-padding
30 power-domains:
35 - description: Padding's clocks
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/freebsd-src/sys/contrib/device-tree/Bindings/usb/
H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhc
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/freebsd-src/sys/contrib/device-tree/Bindings/dsp/
H A Dmediatek,mt8195-dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek mt8195 DSP core
10 - YC Hung <yc.hung@mediatek.com>
13 Some boards from mt8195 contain a DSP core used for
14 advanced pre- and post- audio processing.
18 const: mediatek,mt8195-dsp
22 - description: Address and size of the DSP Cfg registers
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/freebsd-src/sys/contrib/device-tree/Bindings/power/
H A Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Power Domains Controller
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
14 Mediatek processors include support for multiple power domains which can be
15 powered up/down by software based on different application scenes to save power.
17 IP cores belonging to a power domain should contain a 'power-domains'
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/freebsd-src/sys/contrib/device-tree/Bindings/sound/
H A Dmt8195-afe-pcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek AFE PCM controller for mt8195
10 - Trevor Wu <trevor.wu@mediatek.com>
14 const: mediatek,mt8195-audio
25 reset-names:
28 memory-region:
31 Shared memory region for AFE memif. A "shared-dma-pool".
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/freebsd-src/sys/contrib/device-tree/Bindings/net/
H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DWMAC glue layer controller
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
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/freebsd-src/sys/contrib/device-tree/Bindings/soc/mediatek/
H A Dmediatek,mutex.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd-src/sys/contrib/device-tree/Bindings/iommu/
H A Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
35 +----------------+-------
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