xref: /freebsd-src/sys/contrib/device-tree/Bindings/display/mediatek/mediatek,color.yaml (revision 0e8011faf58b743cc652e3b2ad0f7671227610df) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display color processor
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display color processor, namely COLOR, provides hue, luma and
15  saturation adjustments to get better picture quality and to have one panel
16  resemble the other in their output characteristics.
17  COLOR device node must be siblings to the central MMSYS_CONFIG node.
18  For a description of the MMSYS_CONFIG binding, see
19  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
20  for details.
21
22properties:
23  compatible:
24    oneOf:
25      - enum:
26          - mediatek,mt2701-disp-color
27          - mediatek,mt8167-disp-color
28          - mediatek,mt8173-disp-color
29          - mediatek,mt8195-mdp3-color
30      - items:
31          - enum:
32              - mediatek,mt7623-disp-color
33              - mediatek,mt2712-disp-color
34          - const: mediatek,mt2701-disp-color
35      - items:
36          - enum:
37              - mediatek,mt6795-disp-color
38              - mediatek,mt8183-disp-color
39              - mediatek,mt8186-disp-color
40              - mediatek,mt8188-disp-color
41              - mediatek,mt8192-disp-color
42              - mediatek,mt8195-disp-color
43              - mediatek,mt8365-disp-color
44          - const: mediatek,mt8173-disp-color
45  reg:
46    maxItems: 1
47
48  interrupts:
49    maxItems: 1
50
51  power-domains:
52    description: A phandle and PM domain specifier as defined by bindings of
53      the power controller specified by phandle. See
54      Documentation/devicetree/bindings/power/power-domain.yaml for details.
55
56  clocks:
57    items:
58      - description: COLOR Clock
59
60  mediatek,gce-client-reg:
61    description: The register of client driver can be configured by gce with
62      4 arguments defined in this property, such as phandle of gce, subsys id,
63      register offset and size. Each GCE subsys id is mapping to a client
64      defined in the header include/dt-bindings/gce/<chip>-gce.h.
65    $ref: /schemas/types.yaml#/definitions/phandle-array
66    maxItems: 1
67
68required:
69  - compatible
70  - reg
71  - interrupts
72  - power-domains
73  - clocks
74
75additionalProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/interrupt-controller/arm-gic.h>
80    #include <dt-bindings/clock/mt8173-clk.h>
81    #include <dt-bindings/power/mt8173-power.h>
82    #include <dt-bindings/gce/mt8173-gce.h>
83
84    soc {
85        #address-cells = <2>;
86        #size-cells = <2>;
87
88        color0: color@14013000 {
89            compatible = "mediatek,mt8173-disp-color";
90            reg = <0 0x14013000 0 0x1000>;
91            interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
92            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
93            clocks = <&mmsys CLK_MM_DISP_COLOR0>;
94            mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
95        };
96    };
97