/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMParallelDSP.cpp | 488 // ld3 = load i16 489 // sext3 = sext i16 %ld3 to i32 565 auto Ld3 = static_cast<LoadInst*>(PMul1->RHS); in CreateParallelPairs() 568 if (Ld0 == Ld2 || Ld1 == Ld3) in CreateParallelPairs() 572 if (AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) { in CreateParallelPairs() 576 } else if (AreSequentialLoads(Ld3, Ld2, PMul1->VecLd)) { in CreateParallelPairs() 578 LLVM_DEBUG(dbgs() << " exchanging Ld2 and Ld3\n"); in CreateParallelPairs() 583 AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) { in CreateParallelPairs() 563 auto Ld3 = static_cast<LoadInst*>(PMul1->RHS); CreateParallelPairs() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64InstPrinter.cpp | 560 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 }, 561 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 }, 562 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 }, 563 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 }, 564 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 }, 565 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 }, 566 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 }, 567 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 }, 584 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 }, 585 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 }, [all …]
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/freebsd-src/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra20-trimslice.dts | 140 "ld3", "ld4", "ld5", "ld6", "ld7", 254 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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H A D | tegra20-tamonten.dtsi | 130 "ld3", "ld4", "ld5", "ld6", "ld7", 236 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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H A D | tegra20-paz00.dts | 142 "ld3", "ld4", "ld5", "ld6", "ld7", 243 "ld3", "ld4", "ld5", "ld6", "ld7",
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H A D | tegra20-ventana.dts | 154 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 261 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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H A D | tegra20-harmony.dts | 148 "ld3", "ld4", "ld5", "ld6", "ld7", 254 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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H A D | tegra20-seaboard.dts | 153 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 262 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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H A D | tegra20-asus-tf101.dts | 233 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 363 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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H A D | tegra20-acer-a500-picasso.dts | 195 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 305 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
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H A D | tegra20-colibri.dtsi | 210 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
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/freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | nvidia,tegra20-pinmux.yaml | 39 ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12,
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H A D | nvidia,tegra20-pinmux.txt | 78 ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SchedA64FX.td | 2394 def : InstRW<[A64FXWrite_LD3_BH], (instregex "^LD3[BH]")>; 2401 def : InstRW<[A64FXWrite_LD3_WD_IMM], (instregex "^LD3[WD]_IMM")>; 2408 def : InstRW<[A64FXWrite_LD3_WD], (instregex "^LD3[WD]$")>;
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H A D | AArch64SchedA510.td | 1232 def : InstRW<[CortexA510MCWrite<5, 3, CortexA510UnitLdSt>], (instregex "^LD3[BHWD]_IMM$")>; 1235 def : InstRW<[CortexA510MCWrite<5, 3, CortexA510UnitLdSt>], (instregex "^LD3[BHWD]$")>;
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H A D | AArch64SchedKryoDetails.td | 1215 (instregex "LD3(i8|i16|i32)$")>; 1227 (instregex "LD3(i8|i16|i32)_POST$")>;
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H A D | AArch64SchedNeoverseV1.td | 1752 def : InstRW<[V1Write_11c_3L01_3V01], (instregex "^LD3[BHWD]_IMM$")>; 1755 def : InstRW<[V1Write_13c_3L01_1S_3V01], (instregex "^LD3[BHWD]$")>;
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H A D | AArch64InstrInfo.td | 8381 defm LD3 : SIMDLd3Multiple<"ld3">; 8431 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>; 8432 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>; 8433 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>; 8434 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThree [all...] |
H A D | AArch64SchedNeoverseN2.td | 2149 def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^LD3[BHWD]_IMM$")>; 2152 def : InstRW<[N2Write_10cyc_1V_1L_1S], (instregex "^LD3[BHWD]$")>;
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H A D | AArch64SchedNeoverseV2.td | 2667 def : InstRW<[V2Write_9cyc_3L_3V], (instregex "^LD3[BHWD]_IMM$")>; 2670 def : InstRW<[V2Write_10cyc_3V_3L_3S], (instregex "^LD3[BHWD]$")>;
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H A D | AArch64LoadStoreOptimizer.cpp | 1427 // result of a LD3) means that all sub-registers are renamed, potentially in canRenameMOP()
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H A D | AArch64ISelLowering.cpp | 20566 auto *Ld3 = dyn_cast<LoadSDNode>(B.getOperand(1).getOperand(0)); 20567 if (!Ld0 || !Ld1 || !Ld2 || !Ld3 || !Ld0->isSimple() || !Ld1->isSimple() || in replaceZeroVectorStore() 20568 !Ld2->isSimple() || !Ld3->isSimple()) in replaceZeroVectorStore() 20573 Loads.push_back(Ld3); in replaceZeroVectorStore() 19347 auto *Ld3 = dyn_cast<LoadSDNode>(B.getOperand(1).getOperand(0)); isLoadOrMultipleLoads() local [all...] |
/freebsd-src/contrib/llvm-project/clang/include/clang/Basic/ |
H A D | arm_neon.td | 723 def LD3 : WInst<"vld3", "3(c*!)", "QUlQldQdPlQPl">;
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/freebsd-src/contrib/llvm-project/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 4371 .StartsWith("aarch64.sve.ld3", 3) in UpgradeIntrinsicCall()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 6168 llvm_unreachable("Unexpected type for ld3!"); in selectIntrinsicWithSideEffects()
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