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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp486 // ld2 = load i16
487 // sext2 = sext i16 %ld2 to i32
564 auto Ld2 = static_cast<LoadInst*>(PMul0->RHS); in CreateParallelPairs()
568 if (Ld0 == Ld2 || Ld1 == Ld3) in CreateParallelPairs()
572 if (AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) { in CreateParallelPairs()
576 } else if (AreSequentialLoads(Ld3, Ld2, PMul1->VecLd)) { in CreateParallelPairs()
578 LLVM_DEBUG(dbgs() << " exchanging Ld2 and Ld3\n"); in CreateParallelPairs()
583 AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) { in CreateParallelPairs()
562 auto Ld2 = static_cast<LoadInst*>(PMul0->RHS); CreateParallelPairs() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp522 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
523 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
524 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
525 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
526 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
527 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
528 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
529 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
546 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
547 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra20-trimslice.dts139 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
254 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
H A Dtegra20-tamonten.dtsi129 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
236 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
H A Dtegra20-paz00.dts141 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
242 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
H A Dtegra20-ventana.dts154 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
261 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
H A Dtegra20-harmony.dts147 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
254 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
H A Dtegra20-seaboard.dts153 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
262 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
H A Dtegra20-asus-tf101.dts233 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
363 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
H A Dtegra20-acer-a500-picasso.dts195 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
305 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
H A Dtegra20-colibri.dtsi210 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
/freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnvidia,tegra20-pinmux.yaml39 ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12,
H A Dnvidia,tegra20-pinmux.txt78 ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
/freebsd-src/crypto/openssl/crypto/modes/asm/
H A Dghash-ia64.pl322 ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
351 ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
376 { .mfi; ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
396 { .mmi; ld2 $rem[1]=[$rem[1]] //(p19) rem_8bit[rem]
/freebsd-src/contrib/libarchive/libarchive/test/
H A Dtest_read_disk_directory_traversals.c987 assertMakeSymlink("d1/d2/ld2", "../../d2", 1); in test_symlink_logical_loop()
1011 } else if (strcmp(archive_entry_pathname(ae), "l2/d1/d2/ld2") == 0) { in test_symlink_logical_loop()
1014 "l2/d1/d2/ld2/file1") == 0) { in test_symlink_logical_loop()
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DInterleavedAccessPass.cpp28 // It could be transformed into a ld2 intrinsic in AArch64 backend or a vld2
/freebsd-src/sys/dev/mfi/
H A Dmfi.c2762 struct mfi_disk *ld, *ld2; in mfi_check_command_pre() local
2788 TAILQ_FOREACH(ld2, &sc->mfi_ld_tqh, ld_link) { in mfi_check_command_pre()
2789 if (ld2 == ld) in mfi_check_command_pre()
2791 mfi_disk_enable(ld2); in mfi_check_command_pre()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2373 def : InstRW<[A64FXWrite_LD2_BH], (instregex "^LD2[BH]")>;
2380 def : InstRW<[A64FXWrite_LD2_WD_IMM], (instregex "^LD2[WD]_IMM")>;
2387 def : InstRW<[A64FXWrite_LD2_WD], (instregex "^LD2[WD]$")>;
H A DAArch64SchedA510.td1226 def : InstRW<[CortexA510MCWrite<3, 1, CortexA510UnitLdSt>], (instregex "^LD2[BHWD]_IMM$")>;
1229 def : InstRW<[CortexA510MCWrite<3, 2, CortexA510UnitLdSt>], (instregex "^LD2[BHWD]$")>;
H A DAArch64SchedKryoDetails.td1161 (instregex "LD2(i8|i16|i32)$")>;
1167 (instregex "LD2(i8|i16|i32)_POST$")>;
H A DAArch64SchedNeoverseV1.td1745 def : InstRW<[V1Write_8c_2L01_2V01], (instregex "^LD2[BHWD]_IMM$")>;
1749 def : InstRW<[V1Write_9c_2L01_2V01], (instregex "^LD2[BWD]$")>;
H A DAArch64InstrInfo.td8380 defm LD2 : SIMDLd2Multiple<"ld2">;
8427 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
8428 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
8429 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
8430 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwo
[all...]
H A DAArch64SchedNeoverseN2.td2143 def : InstRW<[N2Write_8cyc_1L_1V], (instregex "^LD2[BHWD]_IMM$")>;
2146 def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^LD2[BHWD]$")>;
H A DAArch64SchedNeoverseV2.td2661 def : InstRW<[V2Write_8cyc_2L_2V], (instregex "^LD2[BHWD]_IMM$")>;
2664 def : InstRW<[V2Write_9cyc_2L_2V_2S], (instregex "^LD2[BHWD]$")>;
/freebsd-src/sys/contrib/openzfs/module/icp/asm-aarch64/blake3/
H A Db3_aarch64_sse41.S172 ld2 { v16.4s, v17.4s }, [x8]
1982 ld2 { v19.4s, v20.4s }, [x14]

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