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/llvm-project/mlir/test/Dialect/Affine/SuperVectorize/
H A Dcompose_maps.mlir13 // CHECK: Composed map: (d0) -> (d0)
14 "test_affine_map"() { affine_map = affine_map<(d0) -> (d0 - 1)> } : () -> ()
15 "test_affine_map"() { affine_map = affine_map<(d0) -> (d0 + 1)> } : () -> ()
22 // CHECK: Composed map: (d0)[s0, s1] -> (d0 - s0 + s1)
23 "test_affine_map"() { affine_map = affine_map<(d0)[s0] -> (d0 + s0 - 1)> } : () -> ()
24 "test_affine_map"() { affine_map = affine_map<(d0)[s0] -> (d0 - s0 + 1)> } : () -> ()
31 // CHECK: Composed map: (d0, d1)[s0, s1, s2, s3] -> ((d0 ceildiv s2) * s0, (d1 ceildiv s3) * s1)
32 …"test_affine_map"() { affine_map = affine_map<(d0, d1)[s0, s1] -> (d0 ceildiv s0, d1 ceildiv s1)> …
33 "test_affine_map"() { affine_map = affine_map<(d0, d1)[s0, s1] -> (d0 * s0, d1 * s1)> } : () -> ()
40 // CHECK: Composed map: (d0, d1)[s0, s1] -> (d0 mod s0, d1 mod s1)
[all …]
/llvm-project/llvm/test/MC/ARM/
H A Dneon-vld-vst-align.s5 vld1.8 {d0}, [r4]
6 vld1.8 {d0}, [r4:16]
7 vld1.8 {d0}, [r4:32]
8 vld1.8 {d0}, [r4:64]
9 vld1.8 {d0}, [r4:128]
10 vld1.8 {d0}, [r4:256]
12 @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]
14 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]
17 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]
19 @ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07]
[all …]
H A Ddirective-arch_extension-fp.s35 vselgt.f64 d0, d0, d0
37 vselge.f64 d0, d0, d0
39 vseleq.f64 d0, d0, d0
41 vselvs.f64 d0, d0, d0
43 vmaxnm.f64 d0, d0, d0
45 vminnm.f64 d0, d0, d0
48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
[all …]
H A Dbfloat16-a32-errors2.s2 vfmat.bf16 d0, d0, d0
3 vfmat.bf16 d0, d0, q0
4 vfmat.bf16 d0, q0, d0
5 vfmat.bf16 q0, d0, d0
6 vfmat.bf16 q0, q0, d0
7 vfmat.bf16 q0, d0, q0
8 vfmat.bf16 d0, q0, q0
11 vfmat.bf16 q0, d0, d0[0]
12 vfmat.bf16 d0, q0, d0[0]
13 vfmat.bf16 q0, d0, d0[9]
[all …]
H A Ddirective-arch_extension-simd.s24 vmaxnm.f64 d0, d0, d0
26 vminnm.f64 d0, d0, d0
33 vcvta.s32.f64 s0, d0
35 vcvta.u32.f64 s0, d0
41 vcvtn.s32.f64 s0, d0
43 vcvtn.u32.f64 s0, d0
49 vcvtp.s32.f64 s0, d0
51 vcvtp.u32.f64 s0, d0
57 vcvtm.s32.f64 s0, d0
59 vcvtm.u32.f64 s0, d0
[all …]
H A Dfullfp16-neon.s4 vadd.f16 d0, d1, d2
6 @ ARM: vadd.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x11,0xf2]
8 @ THUMB: vadd.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x02,0x0d]
11 vsub.f16 d0, d1, d2
13 @ ARM: vsub.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x31,0xf2]
15 @ THUMB: vsub.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x02,0x0d]
18 vmul.f16 d0, d1, d2
20 @ ARM: vmul.f16 d0, d1, d2 @ encoding: [0x12,0x0d,0x11,0xf3]
22 @ THUMB: vmul.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0d]
32 vmla.f16 d0, d1, d2
[all …]
H A Dvlstm-vlldm-diag.s7 vlstm r8, {d0 - d11}
8 // ERR: error: operand must be exactly {d0-d15} (T1) or {d0-d31} (T2)
9 // ERR-NEXT: vlstm r8, {d0 - d11}
11 vlldm r8, {d0 - d11}
12 // ERR: error: operand must be exactly {d0-d15} (T1) or {d0-d31} (T2)
13 // ERR-NEXT: vlldm r8, {d0 - d11}
16 // ERR: error: operand must be exactly {d0-d15} (T1) or {d0
[all...]
/llvm-project/mlir/test/Dialect/Affine/
H A Dloop-fusion-slice-computation.mlir10 …: 1, dst loop: 0, depth: 1 : insert point: (1, 1) loop bounds: [(d0) -> (d0), (d0) -> (d0 + 1)] )}}
14 …: 0, dst loop: 1, depth: 1 : insert point: (1, 0) loop bounds: [(d0) -> (d0), (d0) -> (d0 + 1)] )}}
27 …: 1, dst loop: 0, depth: 1 : insert point: (1, 1) loop bounds: [(d0) -> (d0), (d0) -> (d0 + 1)] )}}
31 …: 0, dst loop: 1, depth: 1 : insert point: (1, 0) loop bounds: [(d0) -> (d0), (d0) -> (d0 + 1)] )}}
47 …, dst loop: 0, depth: 1 : insert point: (1, 2) loop bounds: [(d0) -> (d0 + 3), (d0) -> (d0 + 4)] )…
48 %a0 = affine.apply affine_map<(d0) -> (d0 + 2)>(%i0)
52 …, dst loop: 1, depth: 1 : insert point: (1, 0) loop bounds: [(d0) -> (d0 - 3), (d0) -> (d0 - 2)] )…
53 %a1 = affine.apply affine_map<(d0) -> (d0 - 1)>(%i1)
68 …: 0, depth: 1 : insert point: (1, 1) loop bounds: [(d0) -> (d0), (d0) -> (d0 + 1)] [(d0) -> (0), (…
69 …epth: 2 : insert point: (2, 1) loop bounds: [(d0, d1) -> (d0), (d0, d1) -> (d0 + 1)] [(d0, d1) -> …
[all …]
H A Dsimplify-structures.mlir3 // CHECK-DAG: #[[$SET_2D:.*]] = affine_set<(d0, d1) : (d0 - 100 == 0, d1 - 10 == 0, -d0 + 100 >= 0, d1 >= 0)>
4 // CHECK-DAG: #[[$SET_7_11:.*]] = affine_set<(d0, d1) : (d0 * 7 + d1 * 5 + 88 == 0, d0 * 5 - d1 * 11 + 60 == 0, d0 * 11 + d1 * 7 - 24 == 0, d0 * 7 + d1 * 5 + 88 == 0)>
14 affine.if affine_set<(d0, d1) : (2 == 0)>(%arg0, %arg1) {
27 affine.if affine_set<(d0, d
[all...]
H A Dmemref-bound-check.mlir16 %idx0 = affine.apply affine_map<(d0, d1) -> (d0)>(%i, %j)
17 %idx1 = affine.apply affine_map<(d0, d1) -> (d1)>(%i, %j)
25 %idy = affine.apply affine_map<(d0, d1) -> (10*d0 - d1 + 19)>(%i, %j)
48 %idx0 = affine.apply affine_map<(d0, d1, d2) -> (d0 mod 128 + 1)>(%i, %j, %j)
49 %idx1 = affine.apply affine_map<(d0, d1, d2) -> (d1 floordiv 4 + 1)>(%i, %j, %j)
50 %idx2 = affine.apply affine_map<(d0, d1, d2) -> (d2 ceildiv 4)>(%i, %j, %j)
55 %idy0 = affine.apply affine_map<(d0, d1, d2) -> (d0 mod 128)>(%i, %j, %j)
56 %idy1 = affine.apply affine_map<(d0, d1, d2) -> (d1 floordiv 4)>(%i, %j, %j)
57 %idy2 = affine.apply affine_map<(d0, d1, d2) -> (d2 ceildiv 4 - 1)>(%i, %j, %j)
78 %idx0 = affine.apply affine_map<(d0, d1) -> ( 64 * (d0 ceildiv 64))>(%i, %j)
[all …]
/llvm-project/mlir/test/Dialect/GPU/
H A Dmapping.mlir20 … {mapping = [#gpu.loop_dim_map<processor = thread_x, map = (d0) -> (d0), bound = (d0) -> (d0)>,
21 …ME: #gpu.loop_dim_map<processor = thread_y, map = (d0) -> (d0), bound = (d0) -> (d0)>]}
22 … {mapping = [#gpu.loop_dim_map<processor = block_x, map = (d0) -> (d0), bound = (d0) -> (d0)>,
23 …AME: #gpu.loop_dim_map<processor = block_y, map = (d0) -> (d0), bound = (d0) -> (d0)>]}
49 … {mapping = [#gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d0) -> (d0)>,
50 …E: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d0) -> (d0)>,
51 …E: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d0) -> (d0)>,
52 …: #gpu.loop_dim_map<processor = sequential, map = (d0) -> (d0), bound = (d0) -> (d0)>]}
53 … {mapping = [#gpu.loop_dim_map<processor = thread_x, map = (d0) -> (d0), bound = (d0) -> (d0)>,
54 …AME: #gpu.loop_dim_map<processor = thread_y, map = (d0) -> (d0), bound = (d0) -> (d0)>,
[all …]
/llvm-project/llvm/test/TableGen/
H A Dforeach-eval.td6 def d0;
13 dag r1 = !foreach(tmp, d, !subst(d1, d0, !subst(d2, d0,
14 !subst(d3, d0,
15 !subst(d4, d0, tmp)))));
18 !foreach(tmp, tmp2, !subst(d1, d0,
19 !subst(d2, d0,
20 !subst(d3, d0,
21 !subst(d4, d0, tmp))))));
25 // CHECK: dag r1 = (d0 d0, d0, d0, d0);
26 // CHECK: list<dag> r2 = [(d0 d0, d0, d0, d0)];
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dpostlegalizer-lowering-build-vector-to-dup.mir11 liveins: $d0
13 ; LOWER: liveins: $d0
17 ; LOWER-NEXT: $d0 = COPY %build_vector(<8 x s8>)
18 ; LOWER-NEXT: RET_ReallyLR implicit $d0
21 ; SELECT: liveins: $d0
25 ; SELECT-NEXT: $d0 = COPY %build_vector
26 ; SELECT-NEXT: RET_ReallyLR implicit $d0
29 $d0 = COPY %build_vector(<8 x s8>)
30 RET_ReallyLR implicit $d0
39 liveins: $d0,
[all...]
H A Dselect-rev.mir22 liveins: $d0
24 ; CHECK: liveins: $d0
25 ; CHECK: %copy:fpr64 = COPY $d0
27 ; CHECK: $d0 = COPY %rev
28 ; CHECK: RET_ReallyLR implicit $d0
29 %copy:fpr(<2 x s32>) = COPY $d0
31 $d0 = COPY %rev(<2 x s32>)
32 RET_ReallyLR implicit $d0
43 liveins: $d0
45 ; CHECK: liveins: $d0
[all …]
H A Dpostlegalizer-lowering-shuf-to-ins.mir14 liveins: $d0, $d1
23 ; CHECK: liveins: $d0, $d1
24 ; CHECK: %left:_(<2 x s32>) = COPY $d0
29 ; CHECK: $d0 = COPY %shuf(<2 x s32>)
30 ; CHECK: RET_ReallyLR implicit $d0
31 %left:_(<2 x s32>) = COPY $d0
34 $d0 = COPY %shuf(<2 x s32>)
35 RET_ReallyLR implicit $d0
44 liveins: $d0, $d1
53 ; CHECK: liveins: $d0, $d1
[all …]
/llvm-project/llvm/test/MC/M68k/Arith/Classes/
H A DMxCMP_RM.s3 ; CHECK: cmp.b (0,%pc,%d1), %d0
5 cmp.b (0,%pc,%d1), %d0
6 ; CHECK: cmp.b (-1,%pc,%d1), %d0
8 cmp.b (-1,%pc,%d1), %d0
9 ; CHECK: cmp.w (0,%pc,%d1), %d0
11 cmp.w (0,%pc,%d1), %d0
12 ; CHECK: cmp.w (-1,%pc,%d1), %d0
14 cmp.w (-1,%pc,%d1), %d0
15 ; CHECK: cmp.l (0,%pc,%d1), %d0
17 cmp.l (0,%pc,%d1), %d0
[all …]
H A DMxDiMu.s3 ; CHECK: divs %d1, %d0
5 divs %d1, %d0
6 ; CHECK: divu %d1, %d0
8 divu %d1, %d0
9 ; CHECK: divs #0, %d0
11 divs #0, %d0
12 ; CHECK: divu #-1, %d0
14 divu #-1, %d0
15 ; CHECK: divs.l %d1, %d0
17 divs.l %d1, %d0
[all …]
/llvm-project/mlir/test/Dialect/SparseTensor/
H A Droundtrip_encoding.mlir3 #SV = #sparse_tensor.encoding<{ map = (d0) -> (d0 : compressed) }>
5 // CHECK: #[[$SV:.*]] = #sparse_tensor.encoding<{ map = (d0) -> (d0 : compressed) }>
13 map = (d0, d1) -> (d0 : dense, d1 : compressed),
18 // CHECK: #[[$CSR:.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : compressed),…
26 map = (d0, d1) -> (d0 : dense, d1 : compressed),
33 // CHECK: #[[$CSR_OnlyOnes:.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : com…
41 map = (d0, d1) -> (d0 : dense, d1 : compressed),
46 // CHECK: #[[$CSR_OnlyOnes:.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : com…
54 map = (d0, d1) -> (d0 : dense, d1 : compressed),
61 // CHECK: #[[$CSR_OnlyOnes:.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : com…
[all …]
/llvm-project/mlir/test/IR/
H A Daffine-map.mlir15 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1) -> (d0 + 1, d1 * 4 + 2)>
33 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1) -> (d1 - d0 + (d0 - d1 + 1) * 2 + d1 - 1, d1 * 4 + 2…
36 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1) -> (d0 + 2, d1)>
39 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1)[s0] -> (d0 + s0, d1)>
42 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1)[s0] -> (d0 + s0, d1 + 5)>
45 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1)[s0] -> (d0 + d1 + s0, d1)>
48 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1)[s0] -> (d0 + d1 + s0 + 5, d1)>
51 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1)[s0] -> (d0 + d1 + 5, d1)>
54 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1)[s0] -> (d0 + d1 + 5, d1)>
57 // CHECK: #map{{[0-9]*}} = affine_map<(d0, d1)[s0] -> (d0 * 2, d1 * 3)>
[all …]
/llvm-project/mlir/test/python/ir/
H A Daffine_map.py32 d0 = AffineDimExpr.get(0)
36 # CHECK: (d0, d1)[s0, s1, s2] -> ()
40 # CHECK: (d0, d1)[s0, s1, s2] -> (d1, 2)
48 # CHECK: (d0, d1) -> (d0, d1)
49 map3 = AffineMap.get(2, 0, [d0, d1])
52 # CHECK: (d0, d1) -> (d1)
56 # CHECK: (d0, d1, d2) -> (d2, d0, d1)
109 # CHECK: (d0, d1, d2, d3, d4) -> (d1, d2, d3)
113 # CHECK: (d0, d1, d2, d3, d4) -> (d0, d1)
117 # CHECK: (d0, d1, d2, d3, d4) -> (d3, d4)
[all …]
/llvm-project/llvm/test/MC/M68k/Bits/Classes/
H A DMxBTST_MR.s3 ; CHECK: bchg %d0, (%a1)
5 bchg %d0, (%a1)
10 ; CHECK: bclr %d0, (%a1)
12 bclr %d0, (%a1)
17 ; CHECK: bset %d0, (%a1)
19 bset %d0, (%a1)
24 ; CHECK: btst %d0, (%a1)
26 btst %d0, (%a1)
31 ; CHECK: bchg %d0, (%a1)+
33 bchg %d0, (%a1)+
[all …]
/llvm-project/llvm/test/CodeGen/M68k/Arith/
H A Ddivide-by-constant.ll8 ; CHECK-NEXT: move.w (6,%sp), %d0
9 ; CHECK-NEXT: mulu #-1985, %d0
10 ; CHECK-NEXT: lsr.l #8, %d0
11 ; CHECK-NEXT: lsr.l #8, %d0
12 ; CHECK-NEXT: lsr.w #5, %d0
13 ; CHECK-NEXT: and.l #65535, %d0
24 ; CHECK-NEXT: move.w (10,%sp), %d0
25 ; CHECK-NEXT: mulu #-21845, %d0
26 ; CHECK-NEXT: lsr.l #8, %d0
27 ; CHECK-NEXT: lsr.l #8, %d0
[all …]
H A Dbitwise.ll9 ; CHECK-NEXT: move.b (11,%sp), %d0
11 ; CHECK-NEXT: and.b %d0, %d1
12 ; CHECK-NEXT: move.l %d1, %d0
13 ; CHECK-NEXT: and.l #255, %d0
22 ; CHECK-NEXT: move.w (10,%sp), %d0
24 ; CHECK-NEXT: and.w %d0, %d1
25 ; CHECK-NEXT: move.l %d1, %d0
26 ; CHECK-NEXT: and.l #65535, %d0
36 ; CHECK-NEXT: move.l (4,%sp), %d0
37 ; CHECK-NEXT: and.l %d1, %d0
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Darm64-scvt.ll32 ; CHECK-NEXT: ldr d0, [x0]
33 ; CHECK-NEXT: scvtf d0, d0
44 ; CHECK-NEXT: ldr d0, [x0]
45 ; CHECK-NEXT: ucvtf d0, d0
58 ; CHECK-NEXT: scvtf d0, w8
211 ; CHECK-NEXT: ucvtf d0, d0
212 ; CHECK-NEXT: fmul d0, d0, d0
226 ; CHECK-NEXT: ucvtf d0, d0
227 ; CHECK-NEXT: fmul d0, d0, d0
241 ; CHECK-NEXT: ucvtf d0, d0
[all …]
/llvm-project/llvm/test/CodeGen/M68k/Control/
H A Dcmp.ll11 ; CHECK-NEXT: moveq #0, %d0
14 ; CHECK-NEXT: moveq #1, %d0
31 ; CHECK-NEXT: move.l (%a0), %d0
32 ; CHECK-NEXT: and.l #536870911, %d0
33 ; CHECK-NEXT: cmpi.l #0, %d0
36 ; CHECK-NEXT: moveq #0, %d0
39 ; CHECK-NEXT: moveq #1, %d0
57 ; CHECK-NEXT: move.b (%a0), %d0
58 ; CHECK-NEXT: and.b #31, %d0
59 ; CHECK-NEXT: cmpi.b #0, %d0
[all …]

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