1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s 3 4; op reg, reg 5 6define zeroext i8 @andb(i8 zeroext %a, i8 zeroext %b) nounwind { 7; CHECK-LABEL: andb: 8; CHECK: ; %bb.0: 9; CHECK-NEXT: move.b (11,%sp), %d0 10; CHECK-NEXT: move.b (7,%sp), %d1 11; CHECK-NEXT: and.b %d0, %d1 12; CHECK-NEXT: move.l %d1, %d0 13; CHECK-NEXT: and.l #255, %d0 14; CHECK-NEXT: rts 15 %1 = and i8 %a, %b 16 ret i8 %1 17} 18 19define zeroext i16 @andw(i16 zeroext %a, i16 zeroext %b) nounwind { 20; CHECK-LABEL: andw: 21; CHECK: ; %bb.0: 22; CHECK-NEXT: move.w (10,%sp), %d0 23; CHECK-NEXT: move.w (6,%sp), %d1 24; CHECK-NEXT: and.w %d0, %d1 25; CHECK-NEXT: move.l %d1, %d0 26; CHECK-NEXT: and.l #65535, %d0 27; CHECK-NEXT: rts 28 %1 = and i16 %a, %b 29 ret i16 %1 30} 31 32define i32 @andl(i32 %a, i32 %b) nounwind { 33; CHECK-LABEL: andl: 34; CHECK: ; %bb.0: 35; CHECK-NEXT: move.l (8,%sp), %d1 36; CHECK-NEXT: move.l (4,%sp), %d0 37; CHECK-NEXT: and.l %d1, %d0 38; CHECK-NEXT: rts 39 %1 = and i32 %a, %b 40 ret i32 %1 41} 42 43define zeroext i8 @orb(i8 zeroext %a, i8 zeroext %b) nounwind { 44; CHECK-LABEL: orb: 45; CHECK: ; %bb.0: 46; CHECK-NEXT: move.b (11,%sp), %d0 47; CHECK-NEXT: move.b (7,%sp), %d1 48; CHECK-NEXT: or.b %d0, %d1 49; CHECK-NEXT: move.l %d1, %d0 50; CHECK-NEXT: and.l #255, %d0 51; CHECK-NEXT: rts 52 %1 = or i8 %a, %b 53 ret i8 %1 54} 55 56define zeroext i16 @orw(i16 zeroext %a, i16 zeroext %b) nounwind { 57; CHECK-LABEL: orw: 58; CHECK: ; %bb.0: 59; CHECK-NEXT: move.w (10,%sp), %d0 60; CHECK-NEXT: move.w (6,%sp), %d1 61; CHECK-NEXT: or.w %d0, %d1 62; CHECK-NEXT: move.l %d1, %d0 63; CHECK-NEXT: and.l #65535, %d0 64; CHECK-NEXT: rts 65 %1 = or i16 %a, %b 66 ret i16 %1 67} 68 69define i32 @orl(i32 %a, i32 %b) nounwind { 70; CHECK-LABEL: orl: 71; CHECK: ; %bb.0: 72; CHECK-NEXT: move.l (8,%sp), %d1 73; CHECK-NEXT: move.l (4,%sp), %d0 74; CHECK-NEXT: or.l %d1, %d0 75; CHECK-NEXT: rts 76 %1 = or i32 %a, %b 77 ret i32 %1 78} 79 80define zeroext i8 @eorb(i8 zeroext %a, i8 zeroext %b) nounwind { 81; CHECK-LABEL: eorb: 82; CHECK: ; %bb.0: 83; CHECK-NEXT: move.b (11,%sp), %d0 84; CHECK-NEXT: move.b (7,%sp), %d1 85; CHECK-NEXT: eor.b %d0, %d1 86; CHECK-NEXT: move.l %d1, %d0 87; CHECK-NEXT: and.l #255, %d0 88; CHECK-NEXT: rts 89 %1 = xor i8 %a, %b 90 ret i8 %1 91} 92 93define zeroext i16 @eorw(i16 zeroext %a, i16 zeroext %b) nounwind { 94; CHECK-LABEL: eorw: 95; CHECK: ; %bb.0: 96; CHECK-NEXT: move.w (10,%sp), %d0 97; CHECK-NEXT: move.w (6,%sp), %d1 98; CHECK-NEXT: eor.w %d0, %d1 99; CHECK-NEXT: move.l %d1, %d0 100; CHECK-NEXT: and.l #65535, %d0 101; CHECK-NEXT: rts 102 %1 = xor i16 %a, %b 103 ret i16 %1 104} 105 106define i32 @eorl(i32 %a, i32 %b) nounwind { 107; CHECK-LABEL: eorl: 108; CHECK: ; %bb.0: 109; CHECK-NEXT: move.l (8,%sp), %d1 110; CHECK-NEXT: move.l (4,%sp), %d0 111; CHECK-NEXT: eor.l %d1, %d0 112; CHECK-NEXT: rts 113 %1 = xor i32 %a, %b 114 ret i32 %1 115} 116 117; op reg, imm 118; For type i8 and i16, value is loaded from memory to avoid optimizing it to *.l 119 120define void @andib(ptr %a) nounwind { 121; CHECK-LABEL: andib: 122; CHECK: ; %bb.0: 123; CHECK-NEXT: move.l (4,%sp), %a0 124; CHECK-NEXT: move.b (%a0), %d0 125; CHECK-NEXT: and.b #18, %d0 126; CHECK-NEXT: move.b %d0, (%a0) 127; CHECK-NEXT: rts 128 %1 = load i8, ptr %a 129 %2 = and i8 %1, 18 130 store i8 %2, ptr %a 131 ret void 132} 133 134define void @andiw(ptr %a) nounwind { 135; CHECK-LABEL: andiw: 136; CHECK: ; %bb.0: 137; CHECK-NEXT: move.l (4,%sp), %a0 138; CHECK-NEXT: move.w (%a0), %d0 139; CHECK-NEXT: and.w #4660, %d0 140; CHECK-NEXT: move.w %d0, (%a0) 141; CHECK-NEXT: rts 142 %1 = load i16, ptr %a 143 %2 = and i16 %1, 4660 144 store i16 %2, ptr %a 145 ret void 146} 147 148define i32 @andil(i32 %a) nounwind { 149; CHECK-LABEL: andil: 150; CHECK: ; %bb.0: 151; CHECK-NEXT: move.l (4,%sp), %d0 152; CHECK-NEXT: and.l #305419896, %d0 153; CHECK-NEXT: rts 154 %1 = and i32 %a, 305419896 155 ret i32 %1 156} 157 158define void @orib(ptr %a) nounwind { 159; CHECK-LABEL: orib: 160; CHECK: ; %bb.0: 161; CHECK-NEXT: move.l (4,%sp), %a0 162; CHECK-NEXT: move.b (%a0), %d0 163; CHECK-NEXT: or.b #18, %d0 164; CHECK-NEXT: move.b %d0, (%a0) 165; CHECK-NEXT: rts 166 %1 = load i8, ptr %a 167 %2 = or i8 %1, 18 168 store i8 %2, ptr %a 169 ret void 170} 171 172define void @oriw(ptr %a) nounwind { 173; CHECK-LABEL: oriw: 174; CHECK: ; %bb.0: 175; CHECK-NEXT: move.l (4,%sp), %a0 176; CHECK-NEXT: move.w (%a0), %d0 177; CHECK-NEXT: or.w #4660, %d0 178; CHECK-NEXT: move.w %d0, (%a0) 179; CHECK-NEXT: rts 180 %1 = load i16, ptr %a 181 %2 = or i16 %1, 4660 182 store i16 %2, ptr %a 183 ret void 184} 185 186define i32 @oril(i32 %a) nounwind { 187; CHECK-LABEL: oril: 188; CHECK: ; %bb.0: 189; CHECK-NEXT: move.l (4,%sp), %d0 190; CHECK-NEXT: or.l #305419896, %d0 191; CHECK-NEXT: rts 192 %1 = or i32 %a, 305419896 193 ret i32 %1 194} 195 196define void @eorib(ptr %a) nounwind { 197; CHECK-LABEL: eorib: 198; CHECK: ; %bb.0: 199; CHECK-NEXT: move.l (4,%sp), %a0 200; CHECK-NEXT: move.b (%a0), %d0 201; CHECK-NEXT: eori.b #18, %d0 202; CHECK-NEXT: move.b %d0, (%a0) 203; CHECK-NEXT: rts 204 %1 = load i8, ptr %a 205 %2 = xor i8 %1, 18 206 store i8 %2, ptr %a 207 ret void 208} 209 210define void @eoriw(ptr %a) nounwind { 211; CHECK-LABEL: eoriw: 212; CHECK: ; %bb.0: 213; CHECK-NEXT: move.l (4,%sp), %a0 214; CHECK-NEXT: move.w (%a0), %d0 215; CHECK-NEXT: eori.w #4660, %d0 216; CHECK-NEXT: move.w %d0, (%a0) 217; CHECK-NEXT: rts 218 %1 = load i16, ptr %a 219 %2 = xor i16 %1, 4660 220 store i16 %2, ptr %a 221 ret void 222} 223 224define i32 @eoril(i32 %a) nounwind { 225; CHECK-LABEL: eoril: 226; CHECK: ; %bb.0: 227; CHECK-NEXT: move.l (4,%sp), %d0 228; CHECK-NEXT: eori.l #305419896, %d0 229; CHECK-NEXT: rts 230 %1 = xor i32 %a, 305419896 231 ret i32 %1 232} 233 234define i64 @lshr64(i64 %a, i64 %b) nounwind { 235; CHECK-LABEL: lshr64: 236; CHECK: ; %bb.0: 237; CHECK-NEXT: suba.l #12, %sp 238; CHECK-NEXT: movem.l %d2-%d4, (0,%sp) ; 16-byte Folded Spill 239; CHECK-NEXT: move.l (28,%sp), %d3 240; CHECK-NEXT: move.l (16,%sp), %d2 241; CHECK-NEXT: move.l %d3, %d1 242; CHECK-NEXT: add.l #-32, %d1 243; CHECK-NEXT: bmi .LBB18_1 244; CHECK-NEXT: ; %bb.2: 245; CHECK-NEXT: moveq #0, %d0 246; CHECK-NEXT: bra .LBB18_3 247; CHECK-NEXT: .LBB18_1: 248; CHECK-NEXT: move.l %d2, %d0 249; CHECK-NEXT: lsr.l %d3, %d0 250; CHECK-NEXT: .LBB18_3: 251; CHECK-NEXT: move.l %d3, %d4 252; CHECK-NEXT: add.l #-32, %d4 253; CHECK-NEXT: bmi .LBB18_4 254; CHECK-NEXT: ; %bb.5: 255; CHECK-NEXT: lsr.l %d1, %d2 256; CHECK-NEXT: move.l %d2, %d1 257; CHECK-NEXT: bra .LBB18_6 258; CHECK-NEXT: .LBB18_4: 259; CHECK-NEXT: move.l %d3, %d4 260; CHECK-NEXT: eori.l #31, %d4 261; CHECK-NEXT: lsl.l #1, %d2 262; CHECK-NEXT: move.l (20,%sp), %d1 263; CHECK-NEXT: lsl.l %d4, %d2 264; CHECK-NEXT: lsr.l %d3, %d1 265; CHECK-NEXT: or.l %d2, %d1 266; CHECK-NEXT: .LBB18_6: 267; CHECK-NEXT: movem.l (0,%sp), %d2-%d4 ; 16-byte Folded Reload 268; CHECK-NEXT: adda.l #12, %sp 269; CHECK-NEXT: rts 270 %1 = lshr i64 %a, %b 271 ret i64 %1 272} 273 274define i64 @ashr64(i64 %a, i64 %b) nounwind { 275; CHECK-LABEL: ashr64: 276; CHECK: ; %bb.0: 277; CHECK-NEXT: suba.l #8, %sp 278; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill 279; CHECK-NEXT: move.l (24,%sp), %d2 280; CHECK-NEXT: move.l (12,%sp), %d0 281; CHECK-NEXT: move.l %d2, %d3 282; CHECK-NEXT: add.l #-32, %d3 283; CHECK-NEXT: move.l %d2, %d1 284; CHECK-NEXT: add.l #-32, %d1 285; CHECK-NEXT: bmi .LBB19_1 286; CHECK-NEXT: ; %bb.2: 287; CHECK-NEXT: move.l %d0, %d1 288; CHECK-NEXT: asr.l %d3, %d1 289; CHECK-NEXT: bra .LBB19_3 290; CHECK-NEXT: .LBB19_1: 291; CHECK-NEXT: move.l %d2, %d1 292; CHECK-NEXT: eori.l #31, %d1 293; CHECK-NEXT: move.l %d0, %d3 294; CHECK-NEXT: lsl.l #1, %d3 295; CHECK-NEXT: lsl.l %d1, %d3 296; CHECK-NEXT: move.l (16,%sp), %d1 297; CHECK-NEXT: lsr.l %d2, %d1 298; CHECK-NEXT: or.l %d3, %d1 299; CHECK-NEXT: .LBB19_3: 300; CHECK-NEXT: move.l %d2, %d3 301; CHECK-NEXT: add.l #-32, %d3 302; CHECK-NEXT: bmi .LBB19_5 303; CHECK-NEXT: ; %bb.4: 304; CHECK-NEXT: moveq #31, %d2 305; CHECK-NEXT: .LBB19_5: 306; CHECK-NEXT: asr.l %d2, %d0 307; CHECK-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload 308; CHECK-NEXT: adda.l #8, %sp 309; CHECK-NEXT: rts 310 %1 = ashr i64 %a, %b 311 ret i64 %1 312} 313 314define i64 @shl64(i64 %a, i64 %b) nounwind { 315; CHECK-LABEL: shl64: 316; CHECK: ; %bb.0: 317; CHECK-NEXT: suba.l #12, %sp 318; CHECK-NEXT: movem.l %d2-%d4, (0,%sp) ; 16-byte Folded Spill 319; CHECK-NEXT: move.l (28,%sp), %d3 320; CHECK-NEXT: move.l (20,%sp), %d2 321; CHECK-NEXT: move.l %d3, %d0 322; CHECK-NEXT: add.l #-32, %d0 323; CHECK-NEXT: bmi .LBB20_1 324; CHECK-NEXT: ; %bb.2: 325; CHECK-NEXT: moveq #0, %d1 326; CHECK-NEXT: bra .LBB20_3 327; CHECK-NEXT: .LBB20_1: 328; CHECK-NEXT: move.l %d2, %d1 329; CHECK-NEXT: lsl.l %d3, %d1 330; CHECK-NEXT: .LBB20_3: 331; CHECK-NEXT: move.l %d3, %d4 332; CHECK-NEXT: add.l #-32, %d4 333; CHECK-NEXT: bmi .LBB20_4 334; CHECK-NEXT: ; %bb.5: 335; CHECK-NEXT: lsl.l %d0, %d2 336; CHECK-NEXT: move.l %d2, %d0 337; CHECK-NEXT: bra .LBB20_6 338; CHECK-NEXT: .LBB20_4: 339; CHECK-NEXT: move.l %d3, %d4 340; CHECK-NEXT: eori.l #31, %d4 341; CHECK-NEXT: lsr.l #1, %d2 342; CHECK-NEXT: move.l (16,%sp), %d0 343; CHECK-NEXT: lsr.l %d4, %d2 344; CHECK-NEXT: lsl.l %d3, %d0 345; CHECK-NEXT: or.l %d2, %d0 346; CHECK-NEXT: .LBB20_6: 347; CHECK-NEXT: movem.l (0,%sp), %d2-%d4 ; 16-byte Folded Reload 348; CHECK-NEXT: adda.l #12, %sp 349; CHECK-NEXT: rts 350 %1 = shl i64 %a, %b 351 ret i64 %1 352} 353