| /freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | sifive,plic-1.0.0.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
26 with priority below this threshold will not cause the PLIC to raise its
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31 seen while an interrupt handler is active; the PLIC may either queue them or
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, th
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| H A D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
6 specification. The PLIC connects all external interrupts in the system to all
18 with priority below this threshold will not cause the PLIC to raise its
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
31 - compatible : "sifive,plic-1.0.0" and a string identifying the actual
37 - interrupts-extended : Specifies which contexts are connected to the PLIC,
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| H A D | riscv,cpu-intc.txt | 16 via the platform-level interrupt controller (PLIC).
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
|
| /freebsd-src/sys/contrib/device-tree/src/riscv/microchip/ |
| H A D | microchip-mpfs.dtsi | 163 interrupt-parent = <&plic>;
177 plic: interrupt-controller@c000000 { label
178 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
203 interrupt-parent = <&plic>;
215 interrupt-parent = <&plic>;
227 interrupt-parent = <&plic>;
239 interrupt-parent = <&plic>;
251 interrupt-parent = <&plic>;
262 interrupt-parent = <&plic>;
274 interrupt-parent = <&plic>;
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| H A D | mpfs.dtsi | 217 interrupt-parent = <&plic>;
231 plic: interrupt-controller@c000000 { label
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
248 interrupt-parent = <&plic>;
299 interrupt-parent = <&plic>;
311 interrupt-parent = <&plic>;
323 interrupt-parent = <&plic>;
335 interrupt-parent = <&plic>;
347 interrupt-parent = <&plic>;
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| H A D | mpfs-icicle-kit-fabric.dtsi | 23 interrupt-parent = <&plic>;
38 interrupt-parent = <&plic>;
|
| H A D | microchip-mpfs-fabric.dtsi | 20 interrupt-parent = <&plic>;
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| H A D | mpfs-m100pfs-fabric.dtsi | 26 interrupt-parent = <&plic>;
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| H A D | mpfs-polarberry-fabric.dtsi | 26 interrupt-parent = <&plic>;
|
| /freebsd-src/sys/contrib/device-tree/src/riscv/sophgo/ |
| H A D | cv1800b.dtsi | 17 &plic {
18 compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
|
| H A D | cv1812h.dtsi | 18 &plic {
19 compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
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| H A D | cv18xx.dtsi | 52 interrupt-parent = <&plic>;
316 plic: interrupt-controller@70000000 {
178 plic: interrupt-controller@70000000 { global() label
|
| /freebsd-src/sys/contrib/device-tree/src/riscv/allwinner/ |
| H A D | sun20i-d1s.dtsi | 56 interrupt-parent = <&plic>;
66 plic: interrupt-controller@10000000 { label
67 compatible = "allwinner,sun20i-d1-plic",
68 "thead,c900-plic";
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| /freebsd-src/sys/riscv/riscv/ |
| H A D | plic.c | 107 { "sifive,plic-1.0.0", 1 },
108 { "thead,c900-plic", 1 },
245 * From sifive,plic-1.0.0.yaml: in plic_attach()
247 * "The PLIC supports both edge-triggered and level-triggered in plic_attach()
248 * interrupts. For edge-triggered interrupts, the RISC-V PLIC spec in plic_attach()
250 * active; the PLIC may either queue them or ignore them. In the first in plic_attach()
256 * and the T-HEAD C900 PLIC." in plic_attach()
283 device_set_desc(dev, "RISC-V PLIC"); in plic_attach()
351 * This is tricky for a few reasons. The PLIC divides the interrupt in plic_attach()
355 * The tricky part is that the PLIC spe in plic_attach()
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| /freebsd-src/sys/contrib/device-tree/src/riscv/renesas/ |
| H A D | r9a07g043f.dtsi | 55 interrupt-parent = <&plic>;
132 plic: interrupt-controller@12c00000 {
133 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
53 plic: interrupt-controller@12c00000 { global() label
|
| /freebsd-src/sys/contrib/device-tree/src/riscv/starfive/ |
| H A D | jh7100.dtsi | 150 interrupt-parent = <&plic>;
174 plic: interrupt-controller@c000000 {
175 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
170 plic: interrupt-controller@c000000 { global() label
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| /freebsd-src/sys/contrib/device-tree/src/riscv/thead/ |
| H A D | th1520.dtsi | 221 interrupt-parent = <&plic>;
227 plic: interrupt-controller@ffd8000000 {
228 compatible = "thead,th1520-plic", "thead,c900-plic";
164 plic: interrupt-controller@ffd8000000 { global() label
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| /freebsd-src/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | microchip,mpfs-can.yaml | 45 interrupt-parent = <&plic>;
|
| /freebsd-src/sys/contrib/device-tree/Bindings/usb/ |
| H A D | microchip,mpfs-musb.yaml | 60 interrupt-parent = <&plic>;
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| /freebsd-src/sys/contrib/device-tree/Bindings/spi/ |
| H A D | microchip,mpfs-spi.yaml | 83 interrupt-parent = <&plic>;
|
| /freebsd-src/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | microchip,corei2c.yaml | 52 interrupt-parent = <&plic>;
|
| /freebsd-src/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | pwm-sifive.txt | 30 interrupt-parent = <&plic>;
|
| H A D | pwm-sifive.yaml | 69 interrupt-parent = <&plic>;
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| /freebsd-src/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | sifive,gpio.yaml | 82 interrupt-parent = <&plic>;
|
| H A D | microchip,mpfs-gpio.yaml | 82 interrupt-parent = <&plic>;
|