1*c9ccf3a3SEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*c9ccf3a3SEmmanuel Vadot/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3*c9ccf3a3SEmmanuel Vadot 4*c9ccf3a3SEmmanuel Vadot/ { 5*c9ccf3a3SEmmanuel Vadot core_pwm0: pwm@41000000 { 6*c9ccf3a3SEmmanuel Vadot compatible = "microchip,corepwm-rtl-v4"; 7*c9ccf3a3SEmmanuel Vadot reg = <0x0 0x41000000 0x0 0xF0>; 8*c9ccf3a3SEmmanuel Vadot microchip,sync-update-mask = /bits/ 32 <0>; 9*c9ccf3a3SEmmanuel Vadot #pwm-cells = <2>; 10*c9ccf3a3SEmmanuel Vadot clocks = <&fabric_clk3>; 11*c9ccf3a3SEmmanuel Vadot status = "disabled"; 12*c9ccf3a3SEmmanuel Vadot }; 13*c9ccf3a3SEmmanuel Vadot 14*c9ccf3a3SEmmanuel Vadot i2c2: i2c@44000000 { 15*c9ccf3a3SEmmanuel Vadot compatible = "microchip,corei2c-rtl-v7"; 16*c9ccf3a3SEmmanuel Vadot reg = <0x0 0x44000000 0x0 0x1000>; 17*c9ccf3a3SEmmanuel Vadot #address-cells = <1>; 18*c9ccf3a3SEmmanuel Vadot #size-cells = <0>; 19*c9ccf3a3SEmmanuel Vadot clocks = <&fabric_clk3>; 20*c9ccf3a3SEmmanuel Vadot interrupt-parent = <&plic>; 21*c9ccf3a3SEmmanuel Vadot interrupts = <122>; 22*c9ccf3a3SEmmanuel Vadot clock-frequency = <100000>; 23*c9ccf3a3SEmmanuel Vadot status = "disabled"; 24*c9ccf3a3SEmmanuel Vadot }; 25*c9ccf3a3SEmmanuel Vadot 26*c9ccf3a3SEmmanuel Vadot fabric_clk3: fabric-clk3 { 27*c9ccf3a3SEmmanuel Vadot compatible = "fixed-clock"; 28*c9ccf3a3SEmmanuel Vadot #clock-cells = <0>; 29*c9ccf3a3SEmmanuel Vadot clock-frequency = <62500000>; 30*c9ccf3a3SEmmanuel Vadot }; 31*c9ccf3a3SEmmanuel Vadot 32*c9ccf3a3SEmmanuel Vadot fabric_clk1: fabric-clk1 { 33*c9ccf3a3SEmmanuel Vadot compatible = "fixed-clock"; 34*c9ccf3a3SEmmanuel Vadot #clock-cells = <0>; 35*c9ccf3a3SEmmanuel Vadot clock-frequency = <125000000>; 36*c9ccf3a3SEmmanuel Vadot }; 37*c9ccf3a3SEmmanuel Vadot}; 38