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/llvm-project/llvm/test/CodeGen/X86/
H A Dvector-shuffle-masked.ll4 define <4 x i32> @mask_shuffle_v4i32_1234(<4 x i32> %a, <4 x i32> %b, <4 x i32> %passthru, i8 %mask) {
12 %mask.cast = bitcast i8 %mask to <8 x i1>
13 %mask.extract = shufflevector <8 x i1> %mask.cast, <8 x i1> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
14 %res = select <4 x i1> %mask.extract, <4 x i32> %shuffle, <4 x i32> %passthru
18 define <4 x i32> @maskz_shuffle_v4i32_1234(<4 x i32> %a, <4 x i32> %b, i8 %mask) {
25 %mask.cast = bitcast i8 %mask to <8 x i1>
26 %mask
[all...]
/llvm-project/llvm/test/Analysis/CostModel/RISCV/
H A Dactive_lane_mask.ll6 …uction: %mask_nxv16i1_i64 = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 und…
7 …truction: %mask_nxv8i1_i64 = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i64(i64 unde…
8 …truction: %mask_nxv4i1_i64 = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64 unde…
9 …truction: %mask_nxv2i1_i64 = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i64(i64 unde…
10 …truction: %mask_nxv1i1_i64 = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i64(i64 unde…
11 …uction: %mask_nxv16i1_i32 = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 und…
12 …truction: %mask_nxv8i1_i32 = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 unde…
13 …truction: %mask_nxv4i1_i32 = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 unde…
14 …truction: %mask_nxv2i1_i32 = call <vscale x 2 x i1> @llvm.get.active.lane.mask.nxv2i1.i32(i32 unde…
15 …truction: %mask_nxv1i1_i32 = call <vscale x 1 x i1> @llvm.get.active.lane.mask.nxv1i1.i32(i32 unde…
[all …]
/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/
H A Dvid.c230 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], i64 nound…
232 … call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x…
235 vuint8mf8_t test_vid_v_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, size_t vl) { in test_vid_v_u8mf8_tum() argument
236 return __riscv_vid_v_u8mf8_tum(mask, maskedoff, vl); in test_vid_v_u8mf8_tum()
240 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], i64 nound…
242 … call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x…
245 vuint8mf4_t test_vid_v_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, size_t vl) { in test_vid_v_u8mf4_tum() argument
246 return __riscv_vid_v_u8mf4_tum(mask, maskedoff, vl); in test_vid_v_u8mf4_tum()
250 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], i64 nound…
252 … call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x…
[all …]
H A Dvmsne.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsne_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmsne_vv_i8mf8_b64_mu() argument
17 return __riscv_vmsne_vv_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsne_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmsne_vx_i8mf8_b64_mu() argument
27 return __riscv_vmsne_vx_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmseq.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmseq_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmseq_vv_i8mf8_b64_mu() argument
17 return __riscv_vmseq_vv_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmseq_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmseq_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmseq_vx_i8mf8_b64_mu() argument
27 return __riscv_vmseq_vx_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmseq_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsgt.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsgt_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmsgt_vv_i8mf8_b64_mu() argument
17 return __riscv_vmsgt_vv_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsgt_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmsgt_vx_i8mf8_b64_mu() argument
27 return __riscv_vmsgt_vx_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsgt_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmslt.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmslt_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmslt_vv_i8mf8_b64_mu() argument
17 return __riscv_vmslt_vv_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmslt_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmslt_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmslt_vx_i8mf8_b64_mu() argument
27 return __riscv_vmslt_vx_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmslt_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsltu.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …v.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsltu_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8m… in test_vmsltu_vv_u8mf8_b64_mu() argument
17 return __riscv_vmsltu_vv_u8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsltu_vv_u8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 …@llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsltu_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t… in test_vmsltu_vx_u8mf8_b64_mu() argument
27 return __riscv_vmsltu_vx_u8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsltu_vx_u8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …v.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsge.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsge_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmsge_vv_i8mf8_b64_mu() argument
17 return __riscv_vmsge_vv_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsge_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsge_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmsge_vx_i8mf8_b64_mu() argument
27 return __riscv_vmsge_vx_i8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsge_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsgeu.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …v.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsgeu_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8m… in test_vmsgeu_vv_u8mf8_b64_mu() argument
17 return __riscv_vmsgeu_vv_u8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsgeu_vv_u8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 …@llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsgeu_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t… in test_vmsgeu_vx_u8mf8_b64_mu() argument
27 return __riscv_vmsgeu_vx_u8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsgeu_vx_u8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …v.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsleu.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …v.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsleu_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8m… in test_vmsleu_vv_u8mf8_b64_mu() argument
17 return __riscv_vmsleu_vv_u8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsleu_vv_u8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 …@llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsleu_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t… in test_vmsleu_vx_u8mf8_b64_mu() argument
27 return __riscv_vmsleu_vx_u8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsleu_vx_u8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …v.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsgtu.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …v.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsgtu_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8m… in test_vmsgtu_vv_u8mf8_b64_mu() argument
17 return __riscv_vmsgtu_vv_u8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsgtu_vv_u8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 …@llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsgtu_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t… in test_vmsgtu_vx_u8mf8_b64_mu() argument
27 return __riscv_vmsgtu_vx_u8mf8_b64_mu(mask, maskedoff, op1, op2, vl); in test_vmsgtu_vx_u8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …v.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/
H A Dvid.c230 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i8> [[MASKEDOFF:%.*]], i64 nound…
232 … call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8.i64(<vscale x 1 x i8> [[MASKEDOFF]], <vscale x…
235 vuint8mf8_t test_vid_v_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, size_t vl) { in test_vid_v_u8mf8_tum() argument
236 return __riscv_vid_tum(mask, maskedoff, vl); in test_vid_v_u8mf8_tum()
240 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i8> [[MASKEDOFF:%.*]], i64 nound…
242 … call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8.i64(<vscale x 2 x i8> [[MASKEDOFF]], <vscale x…
245 vuint8mf4_t test_vid_v_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, size_t vl) { in test_vid_v_u8mf4_tum() argument
246 return __riscv_vid_tum(mask, maskedoff, vl); in test_vid_v_u8mf4_tum()
250 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i8> [[MASKEDOFF:%.*]], i64 nound…
252 … call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8.i64(<vscale x 4 x i8> [[MASKEDOFF]], <vscale x…
[all …]
H A Dvmsne.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsne_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmsne_vv_i8mf8_b64_mu() argument
17 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsne_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmsne_vx_i8mf8_b64_mu() argument
27 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmseq.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmseq.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmseq_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmseq_vv_i8mf8_b64_mu() argument
17 return __riscv_vmseq_mu(mask, maskedoff, op1, op2, vl); in test_vmseq_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmseq.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmseq_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmseq_vx_i8mf8_b64_mu() argument
27 return __riscv_vmseq_mu(mask, maskedoff, op1, op2, vl); in test_vmseq_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmseq.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsltu.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …v.vmsltu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsltu_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8m… in test_vmsltu_vv_u8mf8_b64_mu() argument
17 return __riscv_vmsltu_mu(mask, maskedoff, op1, op2, vl); in test_vmsltu_vv_u8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 …@llvm.riscv.vmsltu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsltu_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t… in test_vmsltu_vx_u8mf8_b64_mu() argument
27 return __riscv_vmsltu_mu(mask, maskedoff, op1, op2, vl); in test_vmsltu_vx_u8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …v.vmsltu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsgeu.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …v.vmsgeu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsgeu_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8m… in test_vmsgeu_vv_u8mf8_b64_mu() argument
17 return __riscv_vmsgeu_mu(mask, maskedoff, op1, op2, vl); in test_vmsgeu_vv_u8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 …@llvm.riscv.vmsgeu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsgeu_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t… in test_vmsgeu_vx_u8mf8_b64_mu() argument
27 return __riscv_vmsgeu_mu(mask, maskedoff, op1, op2, vl); in test_vmsgeu_vx_u8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …v.vmsgeu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsge.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsge.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsge_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmsge_vv_i8mf8_b64_mu() argument
17 return __riscv_vmsge_mu(mask, maskedoff, op1, op2, vl); in test_vmsge_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsge.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsge_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmsge_vx_i8mf8_b64_mu() argument
27 return __riscv_vmsge_mu(mask, maskedoff, op1, op2, vl); in test_vmsge_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsge.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsleu.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …v.vmsleu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsleu_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8m… in test_vmsleu_vv_u8mf8_b64_mu() argument
17 return __riscv_vmsleu_mu(mask, maskedoff, op1, op2, vl); in test_vmsleu_vv_u8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 …@llvm.riscv.vmsleu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsleu_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t… in test_vmsleu_vx_u8mf8_b64_mu() argument
27 return __riscv_vmsleu_mu(mask, maskedoff, op1, op2, vl); in test_vmsleu_vx_u8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …v.vmsleu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsgt.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsgt_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmsgt_vv_i8mf8_b64_mu() argument
17 return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl); in test_vmsgt_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmsgt_vx_i8mf8_b64_mu() argument
27 return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl); in test_vmsgt_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsle.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsle.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsle_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmsle_vv_i8mf8_b64_mu() argument
17 return __riscv_vmsle_mu(mask, maskedoff, op1, op2, vl); in test_vmsle_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsle.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsle_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmsle_vx_i8mf8_b64_mu() argument
27 return __riscv_vmsle_mu(mask, maskedoff, op1, op2, vl); in test_vmsle_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsle.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmslt.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmslt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmslt_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmslt_vv_i8mf8_b64_mu() argument
17 return __riscv_vmslt_mu(mask, maskedoff, op1, op2, vl); in test_vmslt_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmslt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmslt_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmslt_vx_i8mf8_b64_mu() argument
27 return __riscv_vmslt_mu(mask, maskedoff, op1, op2, vl); in test_vmslt_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmslt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
H A Dvmsgtu.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …v.vmsgtu.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsgtu_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8m… in test_vmsgtu_vv_u8mf8_b64_mu() argument
17 return __riscv_vmsgtu_mu(mask, maskedoff, op1, op2, vl); in test_vmsgtu_vv_u8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 …@llvm.riscv.vmsgtu.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsgtu_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t… in test_vmsgtu_vx_u8mf8_b64_mu() argument
27 return __riscv_vmsgtu_mu(mask, maskedoff, op1, op2, vl); in test_vmsgtu_vx_u8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …v.vmsgtu.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
[all …]
/llvm-project/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/
H A Dvle16.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
13 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vle.mask.nxv1f16.i64(<vscale x 1 x half> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3)
16 vfloat16mf4_t test_vle16_v_f16mf4_m(vbool64_t mask, const _Float16 *base, size_t vl) { in test_vle16_v_f16mf4_m() argument
17 return __riscv_vle16(mask, base, vl); in test_vle16_v_f16mf4_m()
21 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
23 // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vle.mask.nxv2f16.i64(<vscale x 2 x half> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3)
26 vfloat16mf2_t test_vle16_v_f16mf2_m(vbool32_t mask, const _Float16 *base, size_t vl) { in test_vle16_v_f16mf2_m() argument
27 return __riscv_vle16(mask, bas in test_vle16_v_f16mf2_m()
36 test_vle16_v_f16m1_m(vbool16_t mask,const _Float16 * base,size_t vl) test_vle16_v_f16m1_m() argument
46 test_vle16_v_f16m2_m(vbool8_t mask,const _Float16 * base,size_t vl) test_vle16_v_f16m2_m() argument
56 test_vle16_v_f16m4_m(vbool4_t mask,const _Float16 * base,size_t vl) test_vle16_v_f16m4_m() argument
66 test_vle16_v_f16m8_m(vbool2_t mask,const _Float16 * base,size_t vl) test_vle16_v_f16m8_m() argument
76 test_vle16_v_i16mf4_m(vbool64_t mask,const int16_t * base,size_t vl) test_vle16_v_i16mf4_m() argument
86 test_vle16_v_i16mf2_m(vbool32_t mask,const int16_t * base,size_t vl) test_vle16_v_i16mf2_m() argument
96 test_vle16_v_i16m1_m(vbool16_t mask,const int16_t * base,size_t vl) test_vle16_v_i16m1_m() argument
106 test_vle16_v_i16m2_m(vbool8_t mask,const int16_t * base,size_t vl) test_vle16_v_i16m2_m() argument
116 test_vle16_v_i16m4_m(vbool4_t mask,const int16_t * base,size_t vl) test_vle16_v_i16m4_m() argument
126 test_vle16_v_i16m8_m(vbool2_t mask,const int16_t * base,size_t vl) test_vle16_v_i16m8_m() argument
136 test_vle16_v_u16mf4_m(vbool64_t mask,const uint16_t * base,size_t vl) test_vle16_v_u16mf4_m() argument
146 test_vle16_v_u16mf2_m(vbool32_t mask,const uint16_t * base,size_t vl) test_vle16_v_u16mf2_m() argument
156 test_vle16_v_u16m1_m(vbool16_t mask,const uint16_t * base,size_t vl) test_vle16_v_u16m1_m() argument
166 test_vle16_v_u16m2_m(vbool8_t mask,const uint16_t * base,size_t vl) test_vle16_v_u16m2_m() argument
176 test_vle16_v_u16m4_m(vbool4_t mask,const uint16_t * base,size_t vl) test_vle16_v_u16m4_m() argument
186 test_vle16_v_u16m8_m(vbool2_t mask,const uint16_t * base,size_t vl) test_vle16_v_u16m8_m() argument
[all...]
H A Dvle32.c11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*…
13 …cale x 1 x float> @llvm.riscv.vle.mask.nxv1f32.i64(<vscale x 1 x float> poison, ptr [[BASE]], <vsc…
16 vfloat32mf2_t test_vle32_v_f32mf2_m(vbool64_t mask, const float *base, size_t vl) { in test_vle32_v_f32mf2_m() argument
17 return __riscv_vle32(mask, base, vl); in test_vle32_v_f32mf2_m()
21 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*…
23 …cale x 2 x float> @llvm.riscv.vle.mask.nxv2f32.i64(<vscale x 2 x float> poison, ptr [[BASE]], <vsc…
26 vfloat32m1_t test_vle32_v_f32m1_m(vbool32_t mask, const float *base, size_t vl) { in test_vle32_v_f32m1_m() argument
27 return __riscv_vle32(mask, base, vl); in test_vle32_v_f32m1_m()
31 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*…
33 …cale x 4 x float> @llvm.riscv.vle.mask.nxv4f32.i64(<vscale x 4 x float> poison, ptr [[BASE]], <vsc…
[all …]

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