Lines Matching full:mask
11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsne_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_… in test_vmsne_vv_i8mf8_b64_mu() argument
17 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsne_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op… in test_vmsne_vx_i8mf8_b64_mu() argument
27 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
36 vbool32_t test_vmsne_vv_i8mf4_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint8mf4_t op1, vint8mf4_… in test_vmsne_vv_i8mf4_b32_mu() argument
37 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8mf4_b32_mu()
41 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
43 … @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], …
46 vbool32_t test_vmsne_vx_i8mf4_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint8mf4_t op1, int8_t op… in test_vmsne_vx_i8mf4_b32_mu() argument
47 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8mf4_b32_mu()
51 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
53 …cv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscal…
56 vbool16_t test_vmsne_vv_i8mf2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint8mf2_t op1, vint8mf2_… in test_vmsne_vv_i8mf2_b16_mu() argument
57 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8mf2_b16_mu()
61 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
63 … @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], …
66 vbool16_t test_vmsne_vx_i8mf2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint8mf2_t op1, int8_t op… in test_vmsne_vx_i8mf2_b16_mu() argument
67 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8mf2_b16_mu()
71 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
73 …cv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscal…
76 vbool8_t test_vmsne_vv_i8m1_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint8m1_t op1, vint8m1_t op2, … in test_vmsne_vv_i8m1_b8_mu() argument
77 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8m1_b8_mu()
81 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
83 … @llvm.riscv.vmsne.mask.nxv8i8.i8.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], …
86 vbool8_t test_vmsne_vx_i8m1_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint8m1_t op1, int8_t op2, siz… in test_vmsne_vx_i8m1_b8_mu() argument
87 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8m1_b8_mu()
91 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
93 …vmsne.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vsca…
96 vbool4_t test_vmsne_vv_i8m2_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint8m2_t op1, vint8m2_t op2, … in test_vmsne_vv_i8m2_b4_mu() argument
97 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8m2_b4_mu()
101 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
103 …llvm.riscv.vmsne.mask.nxv16i8.i8.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]],…
106 vbool4_t test_vmsne_vx_i8m2_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint8m2_t op1, int8_t op2, siz… in test_vmsne_vx_i8m2_b4_mu() argument
107 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8m2_b4_mu()
111 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
113 …vmsne.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vsca…
116 vbool2_t test_vmsne_vv_i8m4_b2_mu(vbool2_t mask, vbool2_t maskedoff, vint8m4_t op1, vint8m4_t op2, … in test_vmsne_vv_i8m4_b2_mu() argument
117 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8m4_b2_mu()
121 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
123 …llvm.riscv.vmsne.mask.nxv32i8.i8.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]],…
126 vbool2_t test_vmsne_vx_i8m4_b2_mu(vbool2_t mask, vbool2_t maskedoff, vint8m4_t op1, int8_t op2, siz… in test_vmsne_vx_i8m4_b2_mu() argument
127 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8m4_b2_mu()
131 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale…
133 …vmsne.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i1> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vsca…
136 vbool1_t test_vmsne_vv_i8m8_b1_mu(vbool1_t mask, vbool1_t maskedoff, vint8m8_t op1, vint8m8_t op2, … in test_vmsne_vv_i8m8_b1_mu() argument
137 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i8m8_b1_mu()
141 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale…
143 …llvm.riscv.vmsne.mask.nxv64i8.i8.i64(<vscale x 64 x i1> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]],…
146 vbool1_t test_vmsne_vx_i8m8_b1_mu(vbool1_t mask, vbool1_t maskedoff, vint8m8_t op1, int8_t op2, siz… in test_vmsne_vx_i8m8_b1_mu() argument
147 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i8m8_b1_mu()
151 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
153 ….vmsne.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vsca…
156 vbool64_t test_vmsne_vv_i16mf4_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint16mf4_t op1, vint16m… in test_vmsne_vv_i16mf4_b64_mu() argument
157 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i16mf4_b64_mu()
161 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
163 …llvm.riscv.vmsne.mask.nxv1i16.i16.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]],…
166 vbool64_t test_vmsne_vx_i16mf4_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint16mf4_t op1, int16_t… in test_vmsne_vx_i16mf4_b64_mu() argument
167 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i16mf4_b64_mu()
171 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
173 ….vmsne.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vsca…
176 vbool32_t test_vmsne_vv_i16mf2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint16mf2_t op1, vint16m… in test_vmsne_vv_i16mf2_b32_mu() argument
177 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i16mf2_b32_mu()
181 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
183 …llvm.riscv.vmsne.mask.nxv2i16.i16.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]],…
186 vbool32_t test_vmsne_vx_i16mf2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint16mf2_t op1, int16_t… in test_vmsne_vx_i16mf2_b32_mu() argument
187 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i16mf2_b32_mu()
191 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
193 ….vmsne.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vsca…
196 vbool16_t test_vmsne_vv_i16m1_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint16m1_t op1, vint16m1_… in test_vmsne_vv_i16m1_b16_mu() argument
197 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i16m1_b16_mu()
201 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
203 …llvm.riscv.vmsne.mask.nxv4i16.i16.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]],…
206 vbool16_t test_vmsne_vx_i16m1_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint16m1_t op1, int16_t o… in test_vmsne_vx_i16m1_b16_mu() argument
207 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i16m1_b16_mu()
211 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
213 ….vmsne.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vsca…
216 vbool8_t test_vmsne_vv_i16m2_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint16m2_t op1, vint16m2_t op… in test_vmsne_vv_i16m2_b8_mu() argument
217 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i16m2_b8_mu()
221 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
223 …llvm.riscv.vmsne.mask.nxv8i16.i16.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]],…
226 vbool8_t test_vmsne_vx_i16m2_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint16m2_t op1, int16_t op2, … in test_vmsne_vx_i16m2_b8_mu() argument
227 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i16m2_b8_mu()
231 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
233 …sne.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vsc…
236 vbool4_t test_vmsne_vv_i16m4_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint16m4_t op1, vint16m4_t op… in test_vmsne_vv_i16m4_b4_mu() argument
237 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i16m4_b4_mu()
241 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
243 …vm.riscv.vmsne.mask.nxv16i16.i16.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]]…
246 vbool4_t test_vmsne_vx_i16m4_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint16m4_t op1, int16_t op2, … in test_vmsne_vx_i16m4_b4_mu() argument
247 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i16m4_b4_mu()
251 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
253 …sne.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vsc…
256 vbool2_t test_vmsne_vv_i16m8_b2_mu(vbool2_t mask, vbool2_t maskedoff, vint16m8_t op1, vint16m8_t op… in test_vmsne_vv_i16m8_b2_mu() argument
257 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i16m8_b2_mu()
261 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
263 …vm.riscv.vmsne.mask.nxv32i16.i16.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]]…
266 vbool2_t test_vmsne_vx_i16m8_b2_mu(vbool2_t mask, vbool2_t maskedoff, vint16m8_t op1, int16_t op2, … in test_vmsne_vx_i16m8_b2_mu() argument
267 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i16m8_b2_mu()
271 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
273 ….vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vsca…
276 vbool64_t test_vmsne_vv_i32mf2_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint32mf2_t op1, vint32m… in test_vmsne_vv_i32mf2_b64_mu() argument
277 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i32mf2_b64_mu()
281 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
283 …llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]],…
286 vbool64_t test_vmsne_vx_i32mf2_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint32mf2_t op1, int32_t… in test_vmsne_vx_i32mf2_b64_mu() argument
287 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i32mf2_b64_mu()
291 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
293 ….vmsne.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vsca…
296 vbool32_t test_vmsne_vv_i32m1_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint32m1_t op1, vint32m1_… in test_vmsne_vv_i32m1_b32_mu() argument
297 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i32m1_b32_mu()
301 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
303 …llvm.riscv.vmsne.mask.nxv2i32.i32.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]],…
306 vbool32_t test_vmsne_vx_i32m1_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint32m1_t op1, int32_t o… in test_vmsne_vx_i32m1_b32_mu() argument
307 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i32m1_b32_mu()
311 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
313 ….vmsne.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vsca…
316 vbool16_t test_vmsne_vv_i32m2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint32m2_t op1, vint32m2_… in test_vmsne_vv_i32m2_b16_mu() argument
317 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i32m2_b16_mu()
321 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
323 …llvm.riscv.vmsne.mask.nxv4i32.i32.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]],…
326 vbool16_t test_vmsne_vx_i32m2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint32m2_t op1, int32_t o… in test_vmsne_vx_i32m2_b16_mu() argument
327 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i32m2_b16_mu()
331 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
333 ….vmsne.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vsca…
336 vbool8_t test_vmsne_vv_i32m4_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint32m4_t op1, vint32m4_t op… in test_vmsne_vv_i32m4_b8_mu() argument
337 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i32m4_b8_mu()
341 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
343 …llvm.riscv.vmsne.mask.nxv8i32.i32.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]],…
346 vbool8_t test_vmsne_vx_i32m4_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint32m4_t op1, int32_t op2, … in test_vmsne_vx_i32m4_b8_mu() argument
347 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i32m4_b8_mu()
351 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
353 …sne.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vsc…
356 vbool4_t test_vmsne_vv_i32m8_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint32m8_t op1, vint32m8_t op… in test_vmsne_vv_i32m8_b4_mu() argument
357 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i32m8_b4_mu()
361 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
363 …vm.riscv.vmsne.mask.nxv16i32.i32.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]]…
366 vbool4_t test_vmsne_vx_i32m8_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint32m8_t op1, int32_t op2, … in test_vmsne_vx_i32m8_b4_mu() argument
367 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i32m8_b4_mu()
371 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
373 ….vmsne.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vsca…
376 vbool64_t test_vmsne_vv_i64m1_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint64m1_t op1, vint64m1_… in test_vmsne_vv_i64m1_b64_mu() argument
377 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i64m1_b64_mu()
381 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
383 …llvm.riscv.vmsne.mask.nxv1i64.i64.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]],…
386 vbool64_t test_vmsne_vx_i64m1_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint64m1_t op1, int64_t o… in test_vmsne_vx_i64m1_b64_mu() argument
387 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i64m1_b64_mu()
391 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
393 ….vmsne.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vsca…
396 vbool32_t test_vmsne_vv_i64m2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint64m2_t op1, vint64m2_… in test_vmsne_vv_i64m2_b32_mu() argument
397 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i64m2_b32_mu()
401 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
403 …llvm.riscv.vmsne.mask.nxv2i64.i64.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]],…
406 vbool32_t test_vmsne_vx_i64m2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint64m2_t op1, int64_t o… in test_vmsne_vx_i64m2_b32_mu() argument
407 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i64m2_b32_mu()
411 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
413 ….vmsne.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vsca…
416 vbool16_t test_vmsne_vv_i64m4_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint64m4_t op1, vint64m4_… in test_vmsne_vv_i64m4_b16_mu() argument
417 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i64m4_b16_mu()
421 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
423 …llvm.riscv.vmsne.mask.nxv4i64.i64.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]],…
426 vbool16_t test_vmsne_vx_i64m4_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint64m4_t op1, int64_t o… in test_vmsne_vx_i64m4_b16_mu() argument
427 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i64m4_b16_mu()
431 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
433 ….vmsne.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vsca…
436 vbool8_t test_vmsne_vv_i64m8_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint64m8_t op1, vint64m8_t op… in test_vmsne_vv_i64m8_b8_mu() argument
437 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_i64m8_b8_mu()
441 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
443 …llvm.riscv.vmsne.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]],…
446 vbool8_t test_vmsne_vx_i64m8_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint64m8_t op1, int64_t op2, … in test_vmsne_vx_i64m8_b8_mu() argument
447 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_i64m8_b8_mu()
451 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
453 …cv.vmsne.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
456 vbool64_t test_vmsne_vv_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, vuint8mf… in test_vmsne_vv_u8mf8_b64_mu() argument
457 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u8mf8_b64_mu()
461 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
463 … @llvm.riscv.vmsne.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
466 vbool64_t test_vmsne_vx_u8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint8mf8_t op1, uint8_t … in test_vmsne_vx_u8mf8_b64_mu() argument
467 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u8mf8_b64_mu()
471 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
473 …cv.vmsne.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
476 vbool32_t test_vmsne_vv_u8mf4_b32_mu(vbool32_t mask, vbool32_t maskedoff, vuint8mf4_t op1, vuint8mf… in test_vmsne_vv_u8mf4_b32_mu() argument
477 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u8mf4_b32_mu()
481 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
483 … @llvm.riscv.vmsne.mask.nxv2i8.i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], …
486 vbool32_t test_vmsne_vx_u8mf4_b32_mu(vbool32_t mask, vbool32_t maskedoff, vuint8mf4_t op1, uint8_t … in test_vmsne_vx_u8mf4_b32_mu() argument
487 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u8mf4_b32_mu()
491 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
493 …cv.vmsne.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscal…
496 vbool16_t test_vmsne_vv_u8mf2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vuint8mf2_t op1, vuint8mf… in test_vmsne_vv_u8mf2_b16_mu() argument
497 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u8mf2_b16_mu()
501 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
503 … @llvm.riscv.vmsne.mask.nxv4i8.i8.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], …
506 vbool16_t test_vmsne_vx_u8mf2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vuint8mf2_t op1, uint8_t … in test_vmsne_vx_u8mf2_b16_mu() argument
507 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u8mf2_b16_mu()
511 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
513 …cv.vmsne.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscal…
516 vbool8_t test_vmsne_vv_u8m1_b8_mu(vbool8_t mask, vbool8_t maskedoff, vuint8m1_t op1, vuint8m1_t op2… in test_vmsne_vv_u8m1_b8_mu() argument
517 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u8m1_b8_mu()
521 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
523 … @llvm.riscv.vmsne.mask.nxv8i8.i8.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], …
526 vbool8_t test_vmsne_vx_u8m1_b8_mu(vbool8_t mask, vbool8_t maskedoff, vuint8m1_t op1, uint8_t op2, s… in test_vmsne_vx_u8m1_b8_mu() argument
527 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u8m1_b8_mu()
531 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
533 …vmsne.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vsca…
536 vbool4_t test_vmsne_vv_u8m2_b4_mu(vbool4_t mask, vbool4_t maskedoff, vuint8m2_t op1, vuint8m2_t op2… in test_vmsne_vv_u8m2_b4_mu() argument
537 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u8m2_b4_mu()
541 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
543 …llvm.riscv.vmsne.mask.nxv16i8.i8.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]],…
546 vbool4_t test_vmsne_vx_u8m2_b4_mu(vbool4_t mask, vbool4_t maskedoff, vuint8m2_t op1, uint8_t op2, s… in test_vmsne_vx_u8m2_b4_mu() argument
547 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u8m2_b4_mu()
551 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
553 …vmsne.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vsca…
556 vbool2_t test_vmsne_vv_u8m4_b2_mu(vbool2_t mask, vbool2_t maskedoff, vuint8m4_t op1, vuint8m4_t op2… in test_vmsne_vv_u8m4_b2_mu() argument
557 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u8m4_b2_mu()
561 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
563 …llvm.riscv.vmsne.mask.nxv32i8.i8.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]],…
566 vbool2_t test_vmsne_vx_u8m4_b2_mu(vbool2_t mask, vbool2_t maskedoff, vuint8m4_t op1, uint8_t op2, s… in test_vmsne_vx_u8m4_b2_mu() argument
567 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u8m4_b2_mu()
571 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale…
573 …vmsne.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i1> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vsca…
576 vbool1_t test_vmsne_vv_u8m8_b1_mu(vbool1_t mask, vbool1_t maskedoff, vuint8m8_t op1, vuint8m8_t op2… in test_vmsne_vv_u8m8_b1_mu() argument
577 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u8m8_b1_mu()
581 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale…
583 …llvm.riscv.vmsne.mask.nxv64i8.i8.i64(<vscale x 64 x i1> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]],…
586 vbool1_t test_vmsne_vx_u8m8_b1_mu(vbool1_t mask, vbool1_t maskedoff, vuint8m8_t op1, uint8_t op2, s… in test_vmsne_vx_u8m8_b1_mu() argument
587 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u8m8_b1_mu()
591 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
593 ….vmsne.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vsca…
596 vbool64_t test_vmsne_vv_u16mf4_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint16mf4_t op1, vuint1… in test_vmsne_vv_u16mf4_b64_mu() argument
597 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u16mf4_b64_mu()
601 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
603 …llvm.riscv.vmsne.mask.nxv1i16.i16.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]],…
606 vbool64_t test_vmsne_vx_u16mf4_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint16mf4_t op1, uint16… in test_vmsne_vx_u16mf4_b64_mu() argument
607 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u16mf4_b64_mu()
611 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
613 ….vmsne.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vsca…
616 vbool32_t test_vmsne_vv_u16mf2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vuint16mf2_t op1, vuint1… in test_vmsne_vv_u16mf2_b32_mu() argument
617 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u16mf2_b32_mu()
621 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
623 …llvm.riscv.vmsne.mask.nxv2i16.i16.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]],…
626 vbool32_t test_vmsne_vx_u16mf2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vuint16mf2_t op1, uint16… in test_vmsne_vx_u16mf2_b32_mu() argument
627 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u16mf2_b32_mu()
631 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
633 ….vmsne.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vsca…
636 vbool16_t test_vmsne_vv_u16m1_b16_mu(vbool16_t mask, vbool16_t maskedoff, vuint16m1_t op1, vuint16m… in test_vmsne_vv_u16m1_b16_mu() argument
637 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u16m1_b16_mu()
641 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
643 …llvm.riscv.vmsne.mask.nxv4i16.i16.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]],…
646 vbool16_t test_vmsne_vx_u16m1_b16_mu(vbool16_t mask, vbool16_t maskedoff, vuint16m1_t op1, uint16_t… in test_vmsne_vx_u16m1_b16_mu() argument
647 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u16m1_b16_mu()
651 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
653 ….vmsne.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vsca…
656 vbool8_t test_vmsne_vv_u16m2_b8_mu(vbool8_t mask, vbool8_t maskedoff, vuint16m2_t op1, vuint16m2_t … in test_vmsne_vv_u16m2_b8_mu() argument
657 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u16m2_b8_mu()
661 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
663 …llvm.riscv.vmsne.mask.nxv8i16.i16.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]],…
666 vbool8_t test_vmsne_vx_u16m2_b8_mu(vbool8_t mask, vbool8_t maskedoff, vuint16m2_t op1, uint16_t op2… in test_vmsne_vx_u16m2_b8_mu() argument
667 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u16m2_b8_mu()
671 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
673 …sne.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vsc…
676 vbool4_t test_vmsne_vv_u16m4_b4_mu(vbool4_t mask, vbool4_t maskedoff, vuint16m4_t op1, vuint16m4_t … in test_vmsne_vv_u16m4_b4_mu() argument
677 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u16m4_b4_mu()
681 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
683 …vm.riscv.vmsne.mask.nxv16i16.i16.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]]…
686 vbool4_t test_vmsne_vx_u16m4_b4_mu(vbool4_t mask, vbool4_t maskedoff, vuint16m4_t op1, uint16_t op2… in test_vmsne_vx_u16m4_b4_mu() argument
687 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u16m4_b4_mu()
691 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
693 …sne.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vsc…
696 vbool2_t test_vmsne_vv_u16m8_b2_mu(vbool2_t mask, vbool2_t maskedoff, vuint16m8_t op1, vuint16m8_t … in test_vmsne_vv_u16m8_b2_mu() argument
697 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u16m8_b2_mu()
701 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
703 …vm.riscv.vmsne.mask.nxv32i16.i16.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]]…
706 vbool2_t test_vmsne_vx_u16m8_b2_mu(vbool2_t mask, vbool2_t maskedoff, vuint16m8_t op1, uint16_t op2… in test_vmsne_vx_u16m8_b2_mu() argument
707 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u16m8_b2_mu()
711 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
713 ….vmsne.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vsca…
716 vbool64_t test_vmsne_vv_u32mf2_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint32mf2_t op1, vuint3… in test_vmsne_vv_u32mf2_b64_mu() argument
717 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u32mf2_b64_mu()
721 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
723 …llvm.riscv.vmsne.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]],…
726 vbool64_t test_vmsne_vx_u32mf2_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint32mf2_t op1, uint32… in test_vmsne_vx_u32mf2_b64_mu() argument
727 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u32mf2_b64_mu()
731 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
733 ….vmsne.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vsca…
736 vbool32_t test_vmsne_vv_u32m1_b32_mu(vbool32_t mask, vbool32_t maskedoff, vuint32m1_t op1, vuint32m… in test_vmsne_vv_u32m1_b32_mu() argument
737 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u32m1_b32_mu()
741 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
743 …llvm.riscv.vmsne.mask.nxv2i32.i32.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]],…
746 vbool32_t test_vmsne_vx_u32m1_b32_mu(vbool32_t mask, vbool32_t maskedoff, vuint32m1_t op1, uint32_t… in test_vmsne_vx_u32m1_b32_mu() argument
747 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u32m1_b32_mu()
751 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
753 ….vmsne.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vsca…
756 vbool16_t test_vmsne_vv_u32m2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vuint32m2_t op1, vuint32m… in test_vmsne_vv_u32m2_b16_mu() argument
757 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u32m2_b16_mu()
761 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
763 …llvm.riscv.vmsne.mask.nxv4i32.i32.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]],…
766 vbool16_t test_vmsne_vx_u32m2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vuint32m2_t op1, uint32_t… in test_vmsne_vx_u32m2_b16_mu() argument
767 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u32m2_b16_mu()
771 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
773 ….vmsne.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vsca…
776 vbool8_t test_vmsne_vv_u32m4_b8_mu(vbool8_t mask, vbool8_t maskedoff, vuint32m4_t op1, vuint32m4_t … in test_vmsne_vv_u32m4_b8_mu() argument
777 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u32m4_b8_mu()
781 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
783 …llvm.riscv.vmsne.mask.nxv8i32.i32.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]],…
786 vbool8_t test_vmsne_vx_u32m4_b8_mu(vbool8_t mask, vbool8_t maskedoff, vuint32m4_t op1, uint32_t op2… in test_vmsne_vx_u32m4_b8_mu() argument
787 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u32m4_b8_mu()
791 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
793 …sne.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vsc…
796 vbool4_t test_vmsne_vv_u32m8_b4_mu(vbool4_t mask, vbool4_t maskedoff, vuint32m8_t op1, vuint32m8_t … in test_vmsne_vv_u32m8_b4_mu() argument
797 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u32m8_b4_mu()
801 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
803 …vm.riscv.vmsne.mask.nxv16i32.i32.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]]…
806 vbool4_t test_vmsne_vx_u32m8_b4_mu(vbool4_t mask, vbool4_t maskedoff, vuint32m8_t op1, uint32_t op2… in test_vmsne_vx_u32m8_b4_mu() argument
807 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u32m8_b4_mu()
811 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
813 ….vmsne.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vsca…
816 vbool64_t test_vmsne_vv_u64m1_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint64m1_t op1, vuint64m… in test_vmsne_vv_u64m1_b64_mu() argument
817 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u64m1_b64_mu()
821 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
823 …llvm.riscv.vmsne.mask.nxv1i64.i64.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]],…
826 vbool64_t test_vmsne_vx_u64m1_b64_mu(vbool64_t mask, vbool64_t maskedoff, vuint64m1_t op1, uint64_t… in test_vmsne_vx_u64m1_b64_mu() argument
827 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u64m1_b64_mu()
831 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
833 ….vmsne.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vsca…
836 vbool32_t test_vmsne_vv_u64m2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vuint64m2_t op1, vuint64m… in test_vmsne_vv_u64m2_b32_mu() argument
837 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u64m2_b32_mu()
841 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
843 …llvm.riscv.vmsne.mask.nxv2i64.i64.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]],…
846 vbool32_t test_vmsne_vx_u64m2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vuint64m2_t op1, uint64_t… in test_vmsne_vx_u64m2_b32_mu() argument
847 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u64m2_b32_mu()
851 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
853 ….vmsne.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vsca…
856 vbool16_t test_vmsne_vv_u64m4_b16_mu(vbool16_t mask, vbool16_t maskedoff, vuint64m4_t op1, vuint64m… in test_vmsne_vv_u64m4_b16_mu() argument
857 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u64m4_b16_mu()
861 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
863 …llvm.riscv.vmsne.mask.nxv4i64.i64.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]],…
866 vbool16_t test_vmsne_vx_u64m4_b16_mu(vbool16_t mask, vbool16_t maskedoff, vuint64m4_t op1, uint64_t… in test_vmsne_vx_u64m4_b16_mu() argument
867 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u64m4_b16_mu()
871 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
873 ….vmsne.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vsca…
876 vbool8_t test_vmsne_vv_u64m8_b8_mu(vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, vuint64m8_t … in test_vmsne_vv_u64m8_b8_mu() argument
877 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vv_u64m8_b8_mu()
881 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
883 …llvm.riscv.vmsne.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]],…
886 vbool8_t test_vmsne_vx_u64m8_b8_mu(vbool8_t mask, vbool8_t maskedoff, vuint64m8_t op1, uint64_t op2… in test_vmsne_vx_u64m8_b8_mu() argument
887 return __riscv_vmsne_mu(mask, maskedoff, op1, op2, vl); in test_vmsne_vx_u64m8_b8_mu()