11 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
13 …cv.vmsgt.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], <vscal…
16 vbool64_t test_vmsgt_vv_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, vint8mf8_…  in test_vmsgt_vv_i8mf8_b64_mu()  argument
17   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i8mf8_b64_mu()
21 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
23 … @llvm.riscv.vmsgt.mask.nxv1i8.i8.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i8> [[OP1]], …
26 vbool64_t test_vmsgt_vx_i8mf8_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint8mf8_t op1, int8_t op…  in test_vmsgt_vx_i8mf8_b64_mu()  argument
27   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i8mf8_b64_mu()
31 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
33 …cv.vmsgt.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], <vscal…
36 vbool32_t test_vmsgt_vv_i8mf4_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint8mf4_t op1, vint8mf4_…  in test_vmsgt_vv_i8mf4_b32_mu()  argument
37   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i8mf4_b32_mu()
41 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
43 … @llvm.riscv.vmsgt.mask.nxv2i8.i8.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i8> [[OP1]], …
46 vbool32_t test_vmsgt_vx_i8mf4_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint8mf4_t op1, int8_t op…  in test_vmsgt_vx_i8mf4_b32_mu()  argument
47   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i8mf4_b32_mu()
51 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
53 …cv.vmsgt.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], <vscal…
56 vbool16_t test_vmsgt_vv_i8mf2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint8mf2_t op1, vint8mf2_…  in test_vmsgt_vv_i8mf2_b16_mu()  argument
57   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i8mf2_b16_mu()
61 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
63 … @llvm.riscv.vmsgt.mask.nxv4i8.i8.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i8> [[OP1]], …
66 vbool16_t test_vmsgt_vx_i8mf2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint8mf2_t op1, int8_t op…  in test_vmsgt_vx_i8mf2_b16_mu()  argument
67   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i8mf2_b16_mu()
71 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
73 …cv.vmsgt.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], <vscal…
76 vbool8_t test_vmsgt_vv_i8m1_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint8m1_t op1, vint8m1_t op2, …  in test_vmsgt_vv_i8m1_b8_mu()  argument
77   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i8m1_b8_mu()
81 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
83 … @llvm.riscv.vmsgt.mask.nxv8i8.i8.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i8> [[OP1]], …
86 vbool8_t test_vmsgt_vx_i8m1_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint8m1_t op1, int8_t op2, siz…  in test_vmsgt_vx_i8m1_b8_mu()  argument
87   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i8m1_b8_mu()
91 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
93 …vmsgt.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]], <vsca…
96 vbool4_t test_vmsgt_vv_i8m2_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint8m2_t op1, vint8m2_t op2, …  in test_vmsgt_vv_i8m2_b4_mu()  argument
97   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i8m2_b4_mu()
101 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
103 …llvm.riscv.vmsgt.mask.nxv16i8.i8.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i8> [[OP1]],…
106 vbool4_t test_vmsgt_vx_i8m2_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint8m2_t op1, int8_t op2, siz…  in test_vmsgt_vx_i8m2_b4_mu()  argument
107   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i8m2_b4_mu()
111 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
113 …vmsgt.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]], <vsca…
116 vbool2_t test_vmsgt_vv_i8m4_b2_mu(vbool2_t mask, vbool2_t maskedoff, vint8m4_t op1, vint8m4_t op2, …  in test_vmsgt_vv_i8m4_b2_mu()  argument
117   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i8m4_b2_mu()
121 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
123 …llvm.riscv.vmsgt.mask.nxv32i8.i8.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i8> [[OP1]],…
126 vbool2_t test_vmsgt_vx_i8m4_b2_mu(vbool2_t mask, vbool2_t maskedoff, vint8m4_t op1, int8_t op2, siz…  in test_vmsgt_vx_i8m4_b2_mu()  argument
127   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i8m4_b2_mu()
131 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale…
133 …vmsgt.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i1> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]], <vsca…
136 vbool1_t test_vmsgt_vv_i8m8_b1_mu(vbool1_t mask, vbool1_t maskedoff, vint8m8_t op1, vint8m8_t op2, …  in test_vmsgt_vv_i8m8_b1_mu()  argument
137   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i8m8_b1_mu()
141 // CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], <vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale…
143 …llvm.riscv.vmsgt.mask.nxv64i8.i8.i64(<vscale x 64 x i1> [[MASKEDOFF]], <vscale x 64 x i8> [[OP1]],…
146 vbool1_t test_vmsgt_vx_i8m8_b1_mu(vbool1_t mask, vbool1_t maskedoff, vint8m8_t op1, int8_t op2, siz…  in test_vmsgt_vx_i8m8_b1_mu()  argument
147   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i8m8_b1_mu()
151 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
153 ….vmsgt.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]], <vsca…
156 vbool64_t test_vmsgt_vv_i16mf4_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint16mf4_t op1, vint16m…  in test_vmsgt_vv_i16mf4_b64_mu()  argument
157   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i16mf4_b64_mu()
161 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
163 …llvm.riscv.vmsgt.mask.nxv1i16.i16.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i16> [[OP1]],…
166 vbool64_t test_vmsgt_vx_i16mf4_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint16mf4_t op1, int16_t…  in test_vmsgt_vx_i16mf4_b64_mu()  argument
167   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i16mf4_b64_mu()
171 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
173 ….vmsgt.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]], <vsca…
176 vbool32_t test_vmsgt_vv_i16mf2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint16mf2_t op1, vint16m…  in test_vmsgt_vv_i16mf2_b32_mu()  argument
177   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i16mf2_b32_mu()
181 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
183 …llvm.riscv.vmsgt.mask.nxv2i16.i16.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i16> [[OP1]],…
186 vbool32_t test_vmsgt_vx_i16mf2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint16mf2_t op1, int16_t…  in test_vmsgt_vx_i16mf2_b32_mu()  argument
187   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i16mf2_b32_mu()
191 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
193 ….vmsgt.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]], <vsca…
196 vbool16_t test_vmsgt_vv_i16m1_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint16m1_t op1, vint16m1_…  in test_vmsgt_vv_i16m1_b16_mu()  argument
197   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i16m1_b16_mu()
201 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
203 …llvm.riscv.vmsgt.mask.nxv4i16.i16.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i16> [[OP1]],…
206 vbool16_t test_vmsgt_vx_i16m1_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint16m1_t op1, int16_t o…  in test_vmsgt_vx_i16m1_b16_mu()  argument
207   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i16m1_b16_mu()
211 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
213 ….vmsgt.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]], <vsca…
216 vbool8_t test_vmsgt_vv_i16m2_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint16m2_t op1, vint16m2_t op…  in test_vmsgt_vv_i16m2_b8_mu()  argument
217   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i16m2_b8_mu()
221 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
223 …llvm.riscv.vmsgt.mask.nxv8i16.i16.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i16> [[OP1]],…
226 vbool8_t test_vmsgt_vx_i16m2_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint16m2_t op1, int16_t op2, …  in test_vmsgt_vx_i16m2_b8_mu()  argument
227   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i16m2_b8_mu()
231 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
233 …sgt.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]], <vsc…
236 vbool4_t test_vmsgt_vv_i16m4_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint16m4_t op1, vint16m4_t op…  in test_vmsgt_vv_i16m4_b4_mu()  argument
237   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i16m4_b4_mu()
241 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
243 …vm.riscv.vmsgt.mask.nxv16i16.i16.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i16> [[OP1]]…
246 vbool4_t test_vmsgt_vx_i16m4_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint16m4_t op1, int16_t op2, …  in test_vmsgt_vx_i16m4_b4_mu()  argument
247   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i16m4_b4_mu()
251 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
253 …sgt.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]], <vsc…
256 vbool2_t test_vmsgt_vv_i16m8_b2_mu(vbool2_t mask, vbool2_t maskedoff, vint16m8_t op1, vint16m8_t op…  in test_vmsgt_vv_i16m8_b2_mu()  argument
257   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i16m8_b2_mu()
261 // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale…
263 …vm.riscv.vmsgt.mask.nxv32i16.i16.i64(<vscale x 32 x i1> [[MASKEDOFF]], <vscale x 32 x i16> [[OP1]]…
266 vbool2_t test_vmsgt_vx_i16m8_b2_mu(vbool2_t mask, vbool2_t maskedoff, vint16m8_t op1, int16_t op2, …  in test_vmsgt_vx_i16m8_b2_mu()  argument
267   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i16m8_b2_mu()
271 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
273 ….vmsgt.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]], <vsca…
276 vbool64_t test_vmsgt_vv_i32mf2_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint32mf2_t op1, vint32m…  in test_vmsgt_vv_i32mf2_b64_mu()  argument
277   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i32mf2_b64_mu()
281 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
283 …llvm.riscv.vmsgt.mask.nxv1i32.i32.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i32> [[OP1]],…
286 vbool64_t test_vmsgt_vx_i32mf2_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint32mf2_t op1, int32_t…  in test_vmsgt_vx_i32mf2_b64_mu()  argument
287   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i32mf2_b64_mu()
291 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
293 ….vmsgt.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]], <vsca…
296 vbool32_t test_vmsgt_vv_i32m1_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint32m1_t op1, vint32m1_…  in test_vmsgt_vv_i32m1_b32_mu()  argument
297   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i32m1_b32_mu()
301 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
303 …llvm.riscv.vmsgt.mask.nxv2i32.i32.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i32> [[OP1]],…
306 vbool32_t test_vmsgt_vx_i32m1_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint32m1_t op1, int32_t o…  in test_vmsgt_vx_i32m1_b32_mu()  argument
307   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i32m1_b32_mu()
311 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
313 ….vmsgt.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]], <vsca…
316 vbool16_t test_vmsgt_vv_i32m2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint32m2_t op1, vint32m2_…  in test_vmsgt_vv_i32m2_b16_mu()  argument
317   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i32m2_b16_mu()
321 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
323 …llvm.riscv.vmsgt.mask.nxv4i32.i32.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i32> [[OP1]],…
326 vbool16_t test_vmsgt_vx_i32m2_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint32m2_t op1, int32_t o…  in test_vmsgt_vx_i32m2_b16_mu()  argument
327   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i32m2_b16_mu()
331 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
333 ….vmsgt.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]], <vsca…
336 vbool8_t test_vmsgt_vv_i32m4_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint32m4_t op1, vint32m4_t op…  in test_vmsgt_vv_i32m4_b8_mu()  argument
337   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i32m4_b8_mu()
341 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
343 …llvm.riscv.vmsgt.mask.nxv8i32.i32.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i32> [[OP1]],…
346 vbool8_t test_vmsgt_vx_i32m4_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint32m4_t op1, int32_t op2, …  in test_vmsgt_vx_i32m4_b8_mu()  argument
347   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i32m4_b8_mu()
351 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
353 …sgt.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]], <vsc…
356 vbool4_t test_vmsgt_vv_i32m8_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint32m8_t op1, vint32m8_t op…  in test_vmsgt_vv_i32m8_b4_mu()  argument
357   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i32m8_b4_mu()
361 // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale…
363 …vm.riscv.vmsgt.mask.nxv16i32.i32.i64(<vscale x 16 x i1> [[MASKEDOFF]], <vscale x 16 x i32> [[OP1]]…
366 vbool4_t test_vmsgt_vx_i32m8_b4_mu(vbool4_t mask, vbool4_t maskedoff, vint32m8_t op1, int32_t op2, …  in test_vmsgt_vx_i32m8_b4_mu()  argument
367   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i32m8_b4_mu()
371 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
373 ….vmsgt.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]], <vsca…
376 vbool64_t test_vmsgt_vv_i64m1_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint64m1_t op1, vint64m1_…  in test_vmsgt_vv_i64m1_b64_mu()  argument
377   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i64m1_b64_mu()
381 // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x…
383 …llvm.riscv.vmsgt.mask.nxv1i64.i64.i64(<vscale x 1 x i1> [[MASKEDOFF]], <vscale x 1 x i64> [[OP1]],…
386 vbool64_t test_vmsgt_vx_i64m1_b64_mu(vbool64_t mask, vbool64_t maskedoff, vint64m1_t op1, int64_t o…  in test_vmsgt_vx_i64m1_b64_mu()  argument
387   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i64m1_b64_mu()
391 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
393 ….vmsgt.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]], <vsca…
396 vbool32_t test_vmsgt_vv_i64m2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint64m2_t op1, vint64m2_…  in test_vmsgt_vv_i64m2_b32_mu()  argument
397   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i64m2_b32_mu()
401 // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x…
403 …llvm.riscv.vmsgt.mask.nxv2i64.i64.i64(<vscale x 2 x i1> [[MASKEDOFF]], <vscale x 2 x i64> [[OP1]],…
406 vbool32_t test_vmsgt_vx_i64m2_b32_mu(vbool32_t mask, vbool32_t maskedoff, vint64m2_t op1, int64_t o…  in test_vmsgt_vx_i64m2_b32_mu()  argument
407   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i64m2_b32_mu()
411 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
413 ….vmsgt.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]], <vsca…
416 vbool16_t test_vmsgt_vv_i64m4_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint64m4_t op1, vint64m4_…  in test_vmsgt_vv_i64m4_b16_mu()  argument
417   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i64m4_b16_mu()
421 // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x…
423 …llvm.riscv.vmsgt.mask.nxv4i64.i64.i64(<vscale x 4 x i1> [[MASKEDOFF]], <vscale x 4 x i64> [[OP1]],…
426 vbool16_t test_vmsgt_vx_i64m4_b16_mu(vbool16_t mask, vbool16_t maskedoff, vint64m4_t op1, int64_t o…  in test_vmsgt_vx_i64m4_b16_mu()  argument
427   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i64m4_b16_mu()
431 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
433 ….vmsgt.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]], <vsca…
436 vbool8_t test_vmsgt_vv_i64m8_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint64m8_t op1, vint64m8_t op…  in test_vmsgt_vv_i64m8_b8_mu()  argument
437   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vv_i64m8_b8_mu()
441 // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x…
443 …llvm.riscv.vmsgt.mask.nxv8i64.i64.i64(<vscale x 8 x i1> [[MASKEDOFF]], <vscale x 8 x i64> [[OP1]],…
446 vbool8_t test_vmsgt_vx_i64m8_b8_mu(vbool8_t mask, vbool8_t maskedoff, vint64m8_t op1, int64_t op2, …  in test_vmsgt_vx_i64m8_b8_mu()  argument
447   return __riscv_vmsgt_mu(mask, maskedoff, op1, op2, vl);  in test_vmsgt_vx_i64m8_b8_mu()