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/freebsd-src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
/freebsd-src/sys/amd64/amd64/
H A Dbpf_jit_machdep.h40 #define RAX 0
48 #define R8 0
57 #define EAX 0
65 #define R8D 0
74 #define AX 0
83 #define AL 0
89 #define BPF_JIT_FRET 0x01
90 #define BPF_JIT_FPKT 0x02
91 #define BPF_JIT_FMEM 0x04
92 #define BPF_JIT_FJMP 0x08
[all …]
/freebsd-src/sys/i386/i386/
H A Dbpf_jit_machdep.h40 #define EAX 0
49 #define AX 0
58 #define AL 0
64 #define BPF_JIT_FRET 0x01
65 #define BPF_JIT_FPKT 0x02
66 #define BPF_JIT_FMEM 0x04
67 #define BPF_JIT_FJMP 0x08
68 #define BPF_JIT_FADK 0x10
110 emitm(&stream, (11 << 4) | (1 << 3) | (r32 & 0x7), 1); \
112 } while (0)
[all …]
/freebsd-src/sys/crypto/openssl/aarch64/
H A Darmv8-mont.S33 add x29,sp,#0
38 ldr x9,[x2],#8 // bp[0]
40 ldp x7,x8,[x1],#16 // ap[0..1]
44 ldp x13,x14,[x3],#16 // np[0..1]
46 mul x6,x7,x9 // ap[0]*bp[0]
48 umulh x7,x7,x9
49 mul x10,x8,x9 // ap[1]*bp[0]
52 mul x15,x6,x4 // "tp[0]"*n0
55 // (*) mul x12,x13,x15 // np[0]*m1
75 adds x6,x10,x7
[all …]
H A Dpoly1305-armv8.S30 ldp x7,x8,[x1] // load key
31 mov x9,#0xfffffffc0fffffff
32 movk x9,#0x0fff,lsl#48
34 rev x7,x7 // flip bytes
37 and x7,x7,x9 // &=0ffffffc0fffffff
39 and x8,x8,x9 // &=0ffffffc0ffffffc
40 stp x7,x8,[x0,#32] // save key value
45 adr x7,.Lpoly1305_blocks_neon
49 csel x12,x12,x7,eq
74 ldp x7,x8,[x0,#32] // load key value
[all …]
/freebsd-src/crypto/heimdal/lib/wind/
H A Dbidi_table.c9 {0x5be, 1},
10 {0x5c0, 1},
11 {0x5c3, 1},
12 {0x5d0, 0x1b},
13 {0x5f0, 0x5},
14 {0x61b, 1},
15 {0x61f, 1},
16 {0x621, 0x1a},
17 {0x640, 0xb},
18 {0x66d, 0x3},
[all …]
/freebsd-src/sys/arm64/arm64/
H A Dcopyinout.S42 ldr x7, =VM_MAXUSER_ADDRESS
43 cmp x6, x7
69 1: mov x0, xzr /* return 0 */
81 check_user_access 0, 2, copyio_fault_nopcb
85 1: mov x0, xzr /* return 0 */
96 mov x5, xzr /* count = 0 */
98 cbz x2, 3f /* If len == 0 then skip loop */
101 SET_FAULT_HANDLER(x6, x7) /* Set the handler */
103 ldr x7, =VM_MAXUSER_ADDRESS
104 1: cmp x0, x7
[all …]
/freebsd-src/sys/dev/qlnx/qlnxr/
H A Dqlnxr_roce.h47 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1
48 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0
49 #define ROCE_CQE_RESPONDER_TYPE_MASK 0x3
51 #define ROCE_CQE_RESPONDER_INV_FLG_MASK 0x1
53 #define ROCE_CQE_RESPONDER_IMM_FLG_MASK 0x1
55 #define ROCE_CQE_RESPONDER_RDMA_FLG_MASK 0x1
57 #define ROCE_CQE_RESPONDER_RESERVED2_MASK 0x3
71 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1
72 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0
73 #define ROCE_CQE_REQUESTER_TYPE_MASK 0x3
[all …]
/freebsd-src/sys/contrib/libsodium/src/libsodium/crypto_core/hsalsa20/ref2/
H A Dcore_hsalsa20_ref2.c22 uint32_t x0, x1, x2, x3, x4, x5, x6, x7, x8, in crypto_core_hsalsa20() local
27 x0 = U32C(0x61707865); in crypto_core_hsalsa20()
28 x5 = U32C(0x3320646e); in crypto_core_hsalsa20()
29 x10 = U32C(0x79622d32); in crypto_core_hsalsa20()
30 x15 = U32C(0x6b206574); in crypto_core_hsalsa20()
32 x0 = LOAD32_LE(c + 0); in crypto_core_hsalsa20()
37 x1 = LOAD32_LE(k + 0); in crypto_core_hsalsa20()
45 x6 = LOAD32_LE(in + 0); in crypto_core_hsalsa20()
46 x7 = LOAD32_LE(in + 4); in crypto_core_hsalsa20()
50 for (i = ROUNDS; i > 0; i -= 2) { in crypto_core_hsalsa20()
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/bonnell/
H A Dmemory.json4 "Counter": "0,1",
5 "EventCode": "0x5",
8 "UMask": "0x97"
12 "Counter": "0,1",
13 "EventCode": "0x5",
16 "UMask": "0x91"
20 "Counter": "0,1",
21 "EventCode": "0x5",
24 "UMask": "0x9"
28 "Counter": "0,1",
[all …]
/freebsd-src/contrib/googletest/googlemock/test/
H A Dgmock-pp-string_test.cc70 EXPECT_EXPANSION("0", GMOCK_PP_NARG0()); in TEST()
76 EXPECT_EXPANSION("0", GMOCK_PP_HAS_COMMA()); in TEST()
78 EXPECT_EXPANSION("0", GMOCK_PP_HAS_COMMA((, ))); in TEST()
83 EXPECT_EXPANSION("0", GMOCK_PP_IS_EMPTY(, )); in TEST()
84 EXPECT_EXPANSION("0", GMOCK_PP_IS_EMPTY(a)); in TEST()
85 EXPECT_EXPANSION("0", GMOCK_PP_IS_EMPTY(())); in TEST()
93 EXPECT_EXPANSION("2", GMOCK_PP_IF(0, 1, 2)); in TEST()
107 EXPECT_EXPANSION("0", GMOCK_PP_IS_BEGIN_PARENS(sss)); in TEST()
108 EXPECT_EXPANSION("0", GMOCK_PP_IS_BEGIN_PARENS(sss())); in TEST()
109 EXPECT_EXPANSION("0", GMOCK_PP_IS_BEGIN_PARENS(sss() sss)); in TEST()
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/opp/
H A Dqcom-nvmem-cpufreq.txt48 0: MSM8996 V3, speedbin 0
52 4: MSM8996 SG, speedbin 0
62 #size-cells = <0>;
64 CPU0: cpu@0 {
67 reg = <0x0 0x0>;
69 clocks = <&kryocc 0>;
83 reg = <0x0 0x1>;
85 clocks = <&kryocc 0>;
95 reg = <0x0 0x100>;
111 reg = <0x0 0x101>;
[all …]
/freebsd-src/sys/contrib/libsodium/src/libsodium/crypto_core/salsa/ref/
H A Dcore_salsa_ref.c15 uint32_t x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, in crypto_core_salsa() local
21 j0 = x0 = 0x61707865; in crypto_core_salsa()
22 j5 = x5 = 0x3320646e; in crypto_core_salsa()
23 j10 = x10 = 0x79622d32; in crypto_core_salsa()
24 j15 = x15 = 0x6b206574; in crypto_core_salsa()
26 j0 = x0 = LOAD32_LE(c + 0); in crypto_core_salsa()
31 j1 = x1 = LOAD32_LE(k + 0); in crypto_core_salsa()
40 j6 = x6 = LOAD32_LE(in + 0); in crypto_core_salsa()
41 j7 = x7 = LOAD32_LE(in + 4); in crypto_core_salsa()
45 for (i = 0; i < rounds; i += 2) { in crypto_core_salsa()
[all …]
/freebsd-src/sys/dev/iavf/
H A Diavf_adminq_cmd.h43 #define IAVF_FW_API_VERSION_MAJOR 0x0001
44 #define IAVF_FW_API_VERSION_MINOR_X722 0x0006
45 #define IAVF_FW_API_VERSION_MINOR_X710 0x0007
52 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
54 #define IAVF_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
81 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
86 #define IAVF_AQ_FLAG_DD_SHIFT 0
98 #define IAVF_AQ_FLAG_DD (1 << IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
99 #define IAVF_AQ_FLAG_CMP (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
100 #define IAVF_AQ_FLAG_ERR (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
[all …]
/freebsd-src/sys/contrib/device-tree/include/dt-bindings/usb/
H A Dpd.h6 #define PDO_TYPE_FIXED 0
12 #define PDO_TYPE_MASK 0x3
16 #define PDO_VOLT_MASK 0x3ff
17 #define PDO_CURR_MASK 0x3ff
18 #define PDO_PWR_MASK 0x3ff
27 #define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */
40 #define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
52 #define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */
62 #define APDO_TYPE_PPS 0
64 #define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */
[all …]
/freebsd-src/sys/dev/qlnx/qlnxe/
H A Dnvm_cfg.h43 #define NVM_CFG_version 0x83306
54 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
55 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
64 u32 generic_cont0; /* 0x0 */
65 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
66 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
67 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
68 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
69 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
70 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
[all …]

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