Lines Matching +full:0 +full:x7

47 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_MASK  0x1
48 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0
49 #define ROCE_CQE_RESPONDER_TYPE_MASK        0x3
51 #define ROCE_CQE_RESPONDER_INV_FLG_MASK     0x1
53 #define ROCE_CQE_RESPONDER_IMM_FLG_MASK     0x1
55 #define ROCE_CQE_RESPONDER_RDMA_FLG_MASK    0x1
57 #define ROCE_CQE_RESPONDER_RESERVED2_MASK   0x3
71 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_MASK  0x1
72 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0
73 #define ROCE_CQE_REQUESTER_TYPE_MASK        0x3
75 #define ROCE_CQE_REQUESTER_RESERVED5_MASK   0x1F
85 #define ROCE_CQE_COMMON_TOGGLE_BIT_MASK  0x1
86 #define ROCE_CQE_COMMON_TOGGLE_BIT_SHIFT 0
87 #define ROCE_CQE_COMMON_TYPE_MASK        0x3
89 #define ROCE_CQE_COMMON_RESERVED2_MASK   0x1F
161 #define ROCE_RQ_SGE_L_KEY_MASK      0x3FFFFFF
162 #define ROCE_RQ_SGE_L_KEY_SHIFT     0
163 #define ROCE_RQ_SGE_NUM_SGES_MASK   0x7
165 #define ROCE_RQ_SGE_RESERVED0_MASK  0x7
174 #define ROCE_SQ_ATOMIC_WQE_COMP_FLG_MASK       0x1
175 #define ROCE_SQ_ATOMIC_WQE_COMP_FLG_SHIFT      0
176 #define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK   0x1
178 #define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK  0x1
180 #define ROCE_SQ_ATOMIC_WQE_SE_FLG_MASK         0x1
182 #define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_MASK     0x1
184 #define ROCE_SQ_ATOMIC_WQE_RESERVED0_MASK      0x7
203 #define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK       0x1
204 #define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT      0
205 #define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK   0x1
207 #define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK  0x1
209 #define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK         0x1
211 #define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK     0x1
213 #define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK      0x7
241 #define ROCE_SQ_BIND_WQE_COMP_FLG_MASK       0x1
242 #define ROCE_SQ_BIND_WQE_COMP_FLG_SHIFT      0
243 #define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_MASK   0x1
245 #define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_MASK  0x1
247 #define ROCE_SQ_BIND_WQE_SE_FLG_MASK         0x1
249 #define ROCE_SQ_BIND_WQE_INLINE_FLG_MASK     0x1
251 #define ROCE_SQ_BIND_WQE_RESERVED0_MASK      0x7
254 #define ROCE_SQ_BIND_WQE_REMOTE_READ_MASK    0x1
255 #define ROCE_SQ_BIND_WQE_REMOTE_READ_SHIFT   0
256 #define ROCE_SQ_BIND_WQE_REMOTE_WRITE_MASK   0x1
258 #define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_MASK  0x1
260 #define ROCE_SQ_BIND_WQE_LOCAL_READ_MASK     0x1
262 #define ROCE_SQ_BIND_WQE_LOCAL_WRITE_MASK    0x1
264 #define ROCE_SQ_BIND_WQE_RESERVED1_MASK      0x7
268 #define ROCE_SQ_BIND_WQE_ZERO_BASED_MASK     0x1
269 #define ROCE_SQ_BIND_WQE_ZERO_BASED_SHIFT    0
270 #define ROCE_SQ_BIND_WQE_MW_TYPE_MASK        0x1
272 #define ROCE_SQ_BIND_WQE_RESERVED2_MASK      0x3F
289 #define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_MASK       0x1
290 #define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT      0
291 #define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK   0x1
293 #define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK  0x1
295 #define ROCE_SQ_BIND_WQE_1ST_SE_FLG_MASK         0x1
297 #define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_MASK     0x1
299 #define ROCE_SQ_BIND_WQE_1ST_RESERVED0_MASK      0x7
302 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_MASK    0x1
303 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_SHIFT   0
304 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_MASK   0x1
306 #define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_MASK  0x1
308 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_MASK     0x1
310 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_MASK    0x1
312 #define ROCE_SQ_BIND_WQE_1ST_RESERVED1_MASK      0x7
322 #define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_MASK  0x1
323 #define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT 0
324 #define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_MASK     0x1
326 #define ROCE_SQ_BIND_WQE_2ND_RESERVED2_MASK   0x3F
342 #define ROCE_SQ_COMMON_WQE_COMP_FLG_MASK       0x1
343 #define ROCE_SQ_COMMON_WQE_COMP_FLG_SHIFT      0
344 #define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_MASK   0x1
346 #define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_MASK  0x1
348 #define ROCE_SQ_COMMON_WQE_SE_FLG_MASK         0x1
350 #define ROCE_SQ_COMMON_WQE_INLINE_FLG_MASK     0x1
352 #define ROCE_SQ_COMMON_WQE_RESERVED0_MASK      0x7
363 #define ROCE_SQ_FMR_WQE_COMP_FLG_MASK       0x1
364 #define ROCE_SQ_FMR_WQE_COMP_FLG_SHIFT      0
365 #define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_MASK   0x1
367 #define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_MASK  0x1
369 #define ROCE_SQ_FMR_WQE_SE_FLG_MASK         0x1
371 #define ROCE_SQ_FMR_WQE_INLINE_FLG_MASK     0x1
373 #define ROCE_SQ_FMR_WQE_RESERVED0_MASK      0x7
376 #define ROCE_SQ_FMR_WQE_REMOTE_READ_MASK    0x1
377 #define ROCE_SQ_FMR_WQE_REMOTE_READ_SHIFT   0
378 #define ROCE_SQ_FMR_WQE_REMOTE_WRITE_MASK   0x1
380 #define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_MASK  0x1
382 #define ROCE_SQ_FMR_WQE_LOCAL_READ_MASK     0x1
384 #define ROCE_SQ_FMR_WQE_LOCAL_WRITE_MASK    0x1
386 #define ROCE_SQ_FMR_WQE_RESERVED1_MASK      0x7
390 #define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK  0x1F
391 #define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT 0
392 #define ROCE_SQ_FMR_WQE_ZERO_BASED_MASK     0x1
394 #define ROCE_SQ_FMR_WQE_BIND_EN_MASK        0x1
396 #define ROCE_SQ_FMR_WQE_RESERVED2_MASK      0x1
412 #define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_MASK       0x1
413 #define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT      0
414 #define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK   0x1
416 #define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK  0x1
418 #define ROCE_SQ_FMR_WQE_1ST_SE_FLG_MASK         0x1
420 #define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_MASK     0x1
422 #define ROCE_SQ_FMR_WQE_1ST_RESERVED0_MASK      0x7
425 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_MASK    0x1
426 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_SHIFT   0
427 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_MASK   0x1
429 #define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_MASK  0x1
431 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_MASK     0x1
433 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_MASK    0x1
435 #define ROCE_SQ_FMR_WQE_1ST_RESERVED1_MASK      0x7
445 #define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK  0x1F
446 #define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0
447 #define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_MASK     0x1
449 #define ROCE_SQ_FMR_WQE_2ND_BIND_EN_MASK        0x1
451 #define ROCE_SQ_FMR_WQE_2ND_RESERVED2_MASK      0x1
464 #define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_MASK       0x1
465 #define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT      0
466 #define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK   0x1
468 #define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK  0x1
470 #define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_MASK         0x1
472 #define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK     0x1
474 #define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_MASK      0x7
486 #define ROCE_SQ_RDMA_WQE_COMP_FLG_MASK       0x1
487 #define ROCE_SQ_RDMA_WQE_COMP_FLG_SHIFT      0
488 #define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_MASK   0x1
490 #define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_MASK  0x1
492 #define ROCE_SQ_RDMA_WQE_SE_FLG_MASK         0x1
494 #define ROCE_SQ_RDMA_WQE_INLINE_FLG_MASK     0x1
496 #define ROCE_SQ_RDMA_WQE_RESERVED0_MASK      0x7
514 #define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_MASK       0x1
515 #define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT      0
516 #define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK   0x1
518 #define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK  0x1
520 #define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_MASK         0x1
522 #define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK     0x1
524 #define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_MASK      0x7
564 #define ROCE_SQ_SEND_WQE_COMP_FLG_MASK       0x1
565 #define ROCE_SQ_SEND_WQE_COMP_FLG_SHIFT      0
566 #define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_MASK   0x1
568 #define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_MASK  0x1
570 #define ROCE_SQ_SEND_WQE_SE_FLG_MASK         0x1
572 #define ROCE_SQ_SEND_WQE_INLINE_FLG_MASK     0x1
574 #define ROCE_SQ_SEND_WQE_RESERVED0_MASK      0x7
596 #define ROCE_SRQ_SGE_NUM_SGES_MASK   0x3
597 #define ROCE_SRQ_SGE_NUM_SGES_SHIFT  0
598 #define ROCE_SRQ_SGE_RESERVED0_MASK  0x3F
625 #define ROCE_PWM_VAL32_DATA_AGG_CMD_MASK    0x3
626 #define ROCE_PWM_VAL32_DATA_AGG_CMD_SHIFT   0
627 #define ROCE_PWM_VAL32_DATA_BYPASS_EN_MASK  0x1
629 #define ROCE_PWM_VAL32_DATA_RESERVED_MASK   0x1F