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/freebsd-src/sys/contrib/alpine-hal/
H A Dal_hal_pbs_regs.h60 /* [0x0] Conf_bus, Configuration of the SB */
62 /* [0x4] PASW high */
64 /* [0x8] PASW low */
66 /* [0xc] PASW high */
68 /* [0x10] PASW low */
70 /* [0x14] PASW high */
72 /* [0x18] PASW low */
74 /* [0x1c] PASW high */
76 /* [0x20] PASW low */
78 /* [0x24] PASW high */
[all …]
H A Dal_hal_iofic_regs.h73 struct al_iofic_grp_ctrl ctrl[0];
74 uint32_t rsrvd1[0x400 >> 2];
75 struct al_iofic_grp_mod grp_int_mod[0][32];
86 #define INT_CONTROL_GRP_CLEAR_ON_READ (1 << 0)
98 #define INT_CONTROL_GRP_AWID_MASK 0x00000F00
101 #define INT_CONTROL_GRP_MOD_INTV_MASK 0x00FF0000
104 #define INT_CONTROL_GRP_MOD_RES_MASK 0x0F000000
109 #define INT_MOD_INTV_MASK 0x000000FF
110 #define INT_MOD_INTV_SHIFT 0
114 #define INT_MSIX_TGTID_MASK 0x0000FFFF
[all …]
H A Dal_hal_pcie_w_reg.h51 /* [0x0] */
53 /* [0x4] */
55 /* [0x8] */
58 /* [0x10] */
63 /* [0x0] */
65 /* [0x4] */
67 /* [0x8] */
70 /* [0x10] */
72 /* [0x14] */
74 /* [0x18] */
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/virtio/
H A Dpci-iommu.yaml40 BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be
63 reg = <0x0 0x40000000 0x0 0x1000000>;
64 ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;
70 iommu-map = <0x0 &iommu0 0x0 0x8
71 0x9 &iommu0 0x9 0xfff7>;
74 iommu0: iommu@1,0 {
76 reg = <0x800 0 0 0 0>;
85 reg = <0x0 0x50000000 0x0 0x1000000>;
86 ranges = <0x02000000 0x0 0x51000000 0x0 0x51000000 0x0 0x0f000000>;
90 * with endpoint IDs 0x10000 - 0x1ffff
[all …]
/freebsd-src/sys/arm/include/
H A Ddb_machdep.h49 } while (0)
58 #define inst_trap_return(ins) (0)
65 #define inst_return(ins) (((ins) & 0x0e108000) == 0x08108000 || \
66 ((ins) & 0x0ff0fff0) == 0x01a0f000 || \
67 ((ins) & 0x0ffffff0) == 0x012fff10) /* bx */
70 #define inst_call(ins) (((ins) & 0x0f000000) == 0x0b000000)
76 #define inst_branch(ins) (((ins) & 0x0f000000) == 0x0a000000 || \
77 ((ins) & 0x0fdffff0) == 0x079ff100 || \
78 ((ins) & 0x0cd0f000) == 0x0490f000 || \
79 ((ins) & 0x0ffffff0) == 0x012fff30 || /* blx */ \
[all …]
H A Dvfp.h44 #define VFPSID_IMPLEMENTOR_MASK (0xff000000)
45 #define VFPSID_HARDSOFT_IMP (0x00800000)
48 #define VFPSID_SUBVERSION2_MASK (0x000f0000) /* version 1 and 2 */
49 #define VFPSID_SUBVERSION3_MASK (0x007f0000) /* version 3 */
50 #define VFP_ARCH1 0x0
51 #define VFP_ARCH2 0x1
52 #define VFP_ARCH3 0x2
54 #define VFPSID_PARTNUMBER_MASK (0x0000ff00)
56 #define VFPSID_VARIANT_MASK (0x000000f0)
57 #define VFPSID_REVISION_MASK 0x0f
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x0042000
[all...]
/freebsd-src/sys/dev/rtwn/rtl8821a/
H A Dr21a_chan.c64 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00100000, 0); in r21a_bypass_ext_lna_2ghz()
65 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x00400000, 0); in r21a_bypass_ext_lna_2ghz()
66 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x07); in r21a_bypass_ext_lna_2ghz()
67 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), 0, 0x0700); in r21a_bypass_ext_lna_2ghz()
77 0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM); in r21a_set_band_2ghz()
80 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), in r21a_set_band_2ghz()
81 R12A_RFE_PINMUX_LNA_MASK, 0x7000); in r21a_set_band_2ghz()
82 rtwn_bb_setbits(sc, R12A_RFE_PINMUX(0), in r21a_set_band_2ghz()
83 R12A_RFE_PINMUX_PA_A_MASK, 0x70); in r21a_set_band_2ghz()
87 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0, 0x00100000); in r21a_set_band_2ghz()
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385-atl-x530.dts24 reg = <0x00000000 0x40000000>; /* 1GB */
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
29 MBUS_ID(0x01, 0x3d) 0
[all...]
/freebsd-src/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmureg.h29 (((_value) & _flag) != 0)
43 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
55 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
56 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
57 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
58 #define BHND_CCS_FORCE_MASK 0x0000000F
60 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
61 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
62 #define BHND_CCS_AREQ_MASK 0x00000018
64 #define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
[all …]
/freebsd-src/sys/contrib/device-tree/src/mips/loongson/
H A Dloongson3-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
23 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
25 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
29 reg = <0 0x3ff01400 0x64>;
38 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
39 <0x0f000000>, /* int1 */
40 <0x00000000>, /* int2 */
41 <0x00000000>; /* int3 */
[all …]
H A Dloongson64c-package.dtsi10 #address-cells = <0>;
20 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
21 0 0x3ff00000 0 0x3ff00000 0x100000
23 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
25 0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
29 reg = <0 0x3ff01400 0x64>;
38 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
39 <0x0f000000>, /* int1 */
40 <0x00000000>, /* int2 */
41 <0x00000000>; /* int3 */
[all …]
/freebsd-src/sys/dev/sound/pci/
H A Demuxkireg.h50 #define EMU_PTR 0x00
51 #define EMU_PTR_CHNO_MASK 0x0000003f
52 #define EMU_PTR_ADDR_MASK 0x07ff0000
53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000
55 #define EMU_DATA 0x04
57 #define EMU_IPR 0x08
58 #define EMU_IPR_RATETRCHANGE 0x01000000
59 #define EMU_IPR_FXDSP 0x00800000
60 #define EMU_IPR_FORCEINT 0x00400000
61 #define EMU_PCIERROR 0x00200000
[all …]
/freebsd-src/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dloongson,liointc.yaml19 need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
54 pattern: int[0-3]
64 interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
65 and each bit in the cell refers to a child interrupt from 0 to 31.
109 reg = <0x3ff01400 0x64>;
118 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
119 <0x0f000000>, /* int1 */
120 <0x00000000>, /* int2 */
121 <0x00000000>; /* int3 */
/freebsd-src/usr.sbin/bhyve/
H A Dqemu_loader.h20 QEMU_LOADER_ALLOC_FSEG, /* 0x0F000000 - 0x100000 */
38 * including the checksum, have to sum up to 0.
/freebsd-src/contrib/llvm-project/libunwind/include/mach-o/
H A Dcompact_unwind_encoding.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
45 UNWIND_IS_NOT_FUNCTION_START = 0x80000000,
46 UNWIND_HAS_LSDA = 0x40000000,
47 UNWIND_PERSONALITY_MASK = 0x30000000,
60 // 4-bits: 0=old, 1=ebp based, 2=stack-imm, 3=stack-ind, 4=DWARF
71 UNWIND_X86_MODE_MASK = 0x0F000000,
72 UNWIND_X86_MODE_EBP_FRAME = 0x01000000,
73 UNWIND_X86_MODE_STACK_IMMD = 0x02000000,
74 UNWIND_X86_MODE_STACK_IND = 0x03000000,
75 UNWIND_X86_MODE_DWARF = 0x04000000,
[all …]
/freebsd-src/sys/arm/arm/
H A Ddisassem.c76 * m - m register (bits 0-3)
81 * h - 3rd fp operand (register/immediate) (bits 0-4)
83 * t - thumb branch address (bits 24, 0-23)
84 * k - breakpoint comment (bits 0-3, 8-19)
87 * c - comment field bits(0-23)
112 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
113 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
114 { 0x0f000000, 0x0f000000, "swi", "c" },
115 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
116 { 0x0f000000, 0x0a000000, "b", "b" },
[all …]
/freebsd-src/crypto/heimdal/lib/asn1/
H A Dasn1-template.h42 * 0..20 tag
50 * 0..11 type
56 #define A1_OP_MASK (0xf0000000)
57 #define A1_OP_TYPE (0x10000000)
58 #define A1_OP_TYPE_EXTERN (0x20000000)
59 #define A1_OP_TAG (0x30000000)
60 #define A1_OP_PARSE (0x40000000)
61 #define A1_OP_SEQOF (0x50000000)
62 #define A1_OP_SETOF (0x60000000)
63 #define A1_OP_BMEMBER (0x70000000)
[all …]
/freebsd-src/sys/contrib/dev/rtw88/
H A Dphy.h96 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
121 if (chip->rfe_defs_size == 0) in rtw_get_rfe_def()
141 return 0; in rtw_check_supported_rfe()
168 #define MASKBYTE0 0xff
169 #define MASKBYTE1 0xff00
170 #define MASKBYTE2 0xff0000
171 #define MASKBYTE3 0xff000000
172 #define MASKHWORD 0xffff0000
173 #define MASKLWORD 0x0000ffff
174 #define MASKDWORD 0xffffffff
[all …]
/freebsd-src/sys/dev/cxgbe/cudbg/
H A Dcudbg_lib_common.h67 #define CUDBG_EXT_DATA_BIT 0
91 u8 flag; /* bit 0 is used to indicate ext data */
134 (((uint32_t)(data) >> 28) & 0x0000000F) | \
135 (((uint32_t)(data) >> 20) & 0x000000F0) | \
136 (((uint32_t)(data) >> 12) & 0x00000F00) | \
137 (((uint32_t)(data) >> 4) & 0x0000F000) | \
138 (((uint32_t)(data) << 4) & 0x000F0000) | \
139 (((uint32_t)(data) << 12) & 0x00F00000) | \
140 (((uint32_t)(data) << 20) & 0x0F000000) | \
141 (((uint32_t)(data) << 28) & 0xF0000000))
[all …]
/freebsd-src/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_reg.h31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */
32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */
38 #define BHND_PCIE2_CLK_CONTROL 0x000
40 #define BHND_PCIE2_RC_PM_CONTROL 0x004
41 #define BHND_PCIE2_RC_PM_STATUS 0x008
42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C
43 #define BHND_PCIE2_EP_PM_STATUS 0x010
44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014
45 #define BHND_PCIE2_EP_LTR_STATUS 0x018
46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C
[all …]
/freebsd-src/sys/dev/ath/ath_hal/ar5212/
H A Dar5212.ini21 { 0x00001040, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
22 { 0x00001044, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
23 { 0x00001048, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
24 { 0x0000104c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
25 { 0x00001050, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
26 { 0x00001054, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
27 { 0x00001058, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
28 { 0x0000105c, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
29 { 0x00001060, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
30 { 0x00001064, 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f },
[all …]
/freebsd-src/sys/dev/jme/
H A Dif_jmereg.h36 #define VENDORID_JMICRON 0x197B
41 #define DEVICEID_JMC250 0x0250
42 #define DEVICEREVID_JMC250_A0 0x00
43 #define DEVICEREVID_JMC250_A2 0x11
48 #define DEVICEID_JMC260 0x0260
49 #define DEVICEREVID_JMC260_A0 0x00
51 #define DEVICEID_JMC2XX_MASK 0x0FF0
54 #define JME_PCI_BAR0 0x10 /* 16KB memory window. */
56 #define JME_PCI_BAR1 0x18 /* 128bytes I/O window. */
58 #define JME_PCI_BAR2 0x1C /* 256bytes I/O window. */
[all …]

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