| /llvm-project/polly/lib/Transform/ |
| H A D | MaximalStaticExpansion.cpp | 138 SmallPtrSetImpl<MemoryAccess *> &Writes, in isExpandable() argument
150 auto Writes = S.getPHIIncomings(SAI); in isExpandable() local
402 SmallPtrSet<MemoryAccess *, 4> Writes; in expandPhi() local
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| H A D | DeLICM.cpp | 79 isl::union_map Writes, in computeReachingOverwrite() argument
100 isl::union_set Writes, in computeScalarReachingOverwrite() argument
124 isl::set Writes, bool InclPrevWrite, in computeScalarReachingOverwrite() argument
638 auto Writes = getDomainFor(DefMA); computeValueUses() local
[all...] |
| H A D | ZoneAlgo.cpp | 172 isl::union_map Writes, in computeReachingDefinition()
190 isl::union_set Writes, in computeScalarReachingDefinition()
216 isl::set Writes, bool InclDef, in computeScalarReachingDefinition()
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| /llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 426 tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,MutableArrayRef<ReadState> Reads) tryEliminateMoveOrSwap() argument
504 collectWrites(const MCSubtargetInfo & STI,const ReadState & RS,SmallVectorImpl<WriteRef> & Writes,SmallVectorImpl<WriteRef> & CommittedWrites) const collectWrites() argument
571 SmallVector<WriteRef, 4> Writes; checkRAWHazards() local
[all...] |
| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenSchedule.cpp | 762 findRWs(const RecVec & RWDefs,IdxVec & Writes,IdxVec & Reads) const findRWs() argument
881 IdxVec Writes, Reads; collectSchedClasses() local
946 IdxVec Writes; collectSchedClasses() local
1260 IdxVec Writes, Reads; inferFromItinClass() local
1282 IdxVec Writes, Reads; inferFromInstRWs() local
1895 IdxVec Writes, Reads; collectProcResources() local
2052 IdxVec Writes, Reads; collectItinProcResources() local
2090 collectRWResources(ArrayRef<unsigned> Writes,ArrayRef<unsigned> Reads,ArrayRef<unsigned> ProcIndices) collectRWResources() argument
[all...] |
| H A D | CodeGenSchedule.h | 135 IdxVec Writes; global() member
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBundle.h | 224 bool Writes; member
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | CalcSpillWeights.cpp | 270 bool Reads, Writes; weightCalcHelper() local
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| H A D | MLRegAllocEvictAdvisor.cpp | 817 bool Reads, Writes; getLIFeatureComponents() local
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| H A D | RegisterCoalescer.cpp | 1849 bool Reads, Writes; updateRegDefsUses() local
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| H A D | MachinePipeliner.cpp | 2990 bool Reads, Writes; orderDependence() local
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| /llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopDataPrefetch.cpp | 240 bool Writes = false; global() member
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| /llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 376 void setDependentWrites(unsigned Writes) { in setDependentWrites()
448 SmallVector<WriteDescriptor, 2> Writes; // Implicit writes are at the end. member
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| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 604 bool Reads, Writes; SafeInFPUDelaySlot() local
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| /llvm-project/polly/lib/Support/ |
| H A D | ISLTools.cpp | 314 isl::union_map Writes, bool Reverse, in computeReachingWrite()
366 polly::computeArrayUnused(isl::union_map Schedule, isl::union_map Writes, in computeArrayUnused()
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMParallelDSP.cpp | 341 SmallVector<Instruction*, 8> Writes; RecordMemoryOps() local
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| /llvm-project/polly/lib/Analysis/ |
| H A D | ScopBuilder.cpp | 2636 isl::union_map Writes = scop->getWrites(); hoistInvariantLoads() local
2680 hasNonHoistableBasePtrInScop(MemoryAccess * MA,isl::union_map Writes) hasNonHoistableBasePtrInScop() argument
2735 getNonHoistableCtx(MemoryAccess * Access,isl::union_map Writes) getNonHoistableCtx() argument
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| /llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | ELF_riscv.cpp | 497 SmallVector<uint32_t, 0> Writes; member
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| /llvm-project/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 1093 IdxVec Writes = SC.Writes; GenSchedClassTables() local
|