Home
last modified time | relevance | path

Searched defs:VirtReg (Results 1 – 25 of 32) sorted by relevance

12

/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) { in assign() argument
121 void LiveRegMatrix::unassign(const LiveInterval &VirtReg) { in unassign() argument
146 checkRegMaskInterference(const LiveInterval & VirtReg,MCRegister PhysReg) checkRegMaskInterference() argument
164 checkRegUnitInterference(const LiveInterval & VirtReg,MCRegister PhysReg) checkRegUnitInterference() argument
186 checkInterference(const LiveInterval & VirtReg,MCRegister PhysReg) checkInterference() argument
[all...]
H A DRegAllocFast.cpp205 Register VirtReg; ///< Virtual register number. global() member
368 findLiveVirtReg(Register VirtReg) findLiveVirtReg() argument
439 getStackSpaceFor(Register VirtReg) getStackSpaceFor() argument
467 mayLiveOut(Register VirtReg) mayLiveOut() argument
520 mayLiveIn(Register VirtReg) mayLiveIn() argument
539 spill(MachineBasicBlock::iterator Before,Register VirtReg,MCPhysReg AssignedReg,bool Kill,bool LiveOut) spill() argument
599 reload(MachineBasicBlock::iterator Before,Register VirtReg,MCPhysReg PhysReg) reload() argument
704 switch (unsigned VirtReg = RegUnitStates[Unit]) { displacePhysReg() local
733 switch (unsigned VirtReg = RegUnitStates[FirstUnit]) { freePhysReg() local
758 switch (unsigned VirtReg = RegUnitStates[Unit]) { calcSpillCost() local
776 assignDanglingDebugValues(MachineInstr & Definition,Register VirtReg,MCPhysReg Reg) assignDanglingDebugValues() argument
814 Register VirtReg = LR.VirtReg; assignVirtToPhysReg() local
866 const Register VirtReg = LR.VirtReg; allocVirtReg() local
955 Register VirtReg = MO.getReg(); allocVirtRegUndef() local
984 defineLiveThroughVirtReg(MachineInstr & MI,unsigned OpNum,Register VirtReg) defineLiveThroughVirtReg() argument
1020 defineVirtReg(MachineInstr & MI,unsigned OpNum,Register VirtReg,bool LookAtPhysRegUses) defineVirtReg() argument
1098 useVirtReg(MachineInstr & MI,MachineOperand & MO,Register VirtReg) useVirtReg() argument
1196 switch (unsigned VirtReg = RegUnitStates[Unit]) { dumpState() local
1224 Register VirtReg = LR.VirtReg; dumpState() local
[all...]
H A DRegAllocGreedy.cpp236 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg() argument
251 LRE_WillShrinkVirtReg(Register VirtReg) LRE_WillShrinkVirtReg() argument
399 tryAssign(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,const SmallVirtRegSet & FixedRegisters) tryAssign() argument
457 canReassign(const LiveInterval & VirtReg,MCRegister FromReg) const canReassign() argument
483 evictInterference(const LiveInterval & VirtReg,MCRegister PhysReg,SmallVectorImpl<Register> & NewVRegs) evictInterference() argument
533 getOrderLimit(const LiveInterval & VirtReg,const AllocationOrder & Order,unsigned CostPerUseLimit) const getOrderLimit() argument
579 tryEvict(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) tryEvict() argument
1062 tryRegionSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryRegionSplit() argument
1173 calculateRegionSplitCost(const LiveInterval & VirtReg,AllocationOrder & Order,BlockFrequency & BestCost,unsigned & NumCands,bool IgnoreCSR) calculateRegionSplitCost() argument
1191 doRegionSplit(const LiveInterval & VirtReg,unsigned BestCand,bool HasCompact,SmallVectorImpl<Register> & NewVRegs) doRegionSplit() argument
1234 trySplitAroundHintReg(MCPhysReg Hint,const LiveInterval & VirtReg,SmallVectorImpl<Register> & NewVRegs,AllocationOrder & Order) trySplitAroundHintReg() argument
1295 tryBlockSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryBlockSplit() argument
1384 readsLaneSubset(const MachineRegisterInfo & MRI,const MachineInstr * MI,const LiveInterval & VirtReg,const TargetRegisterInfo * TRI,SlotIndex Use,const TargetInstrInfo * TII) readsLaneSubset() argument
1416 tryInstructionSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryInstructionSplit() argument
1569 tryLocalSplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs) tryLocalSplit() argument
1800 trySplit(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,const SmallVirtRegSet & FixedRegisters) trySplit() argument
1870 mayRecolorAllInterferences(MCRegister PhysReg,const LiveInterval & VirtReg,SmallLISet & RecoloringCandidates,const SmallVirtRegSet & FixedRegisters) mayRecolorAllInterferences() argument
1956 tryLastChanceRecoloring(const LiveInterval & VirtReg,AllocationOrder & Order,SmallVectorImpl<Register> & NewVRegs,SmallVirtRegSet & FixedRegisters,RecoloringStack & RecolorStack,unsigned Depth) tryLastChanceRecoloring() argument
2144 selectOrSplit(const LiveInterval & VirtReg,SmallVectorImpl<Register> & NewVRegs) selectOrSplit() argument
2177 tryAssignCSRFirstTime(const LiveInterval & VirtReg,AllocationOrder & Order,MCRegister PhysReg,uint8_t & CostPerUseLimit,SmallVectorImpl<Register> & NewVRegs) tryAssignCSRFirstTime() argument
2285 tryHintRecoloring(const LiveInterval & VirtReg) tryHintRecoloring() argument
2410 selectOrSplitImpl(const LiveInterval & VirtReg,SmallVectorImpl<Register> & NewVRegs,SmallVirtRegSet & FixedRegisters,RecoloringStack & RecolorStack,unsigned Depth) selectOrSplitImpl() argument
[all...]
H A DRegAllocBasic.cpp161 void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg() argument
208 spillInterferences(const LiveInterval & VirtReg,MCRegister PhysReg,SmallVectorImpl<Register> & SplitVRegs) spillInterferences() argument
259 selectOrSplit(const LiveInterval & VirtReg,SmallVectorImpl<Register> & SplitVRegs) selectOrSplit() argument
[all...]
H A DRegAllocEvictionAdvisor.cpp168 canEvictHintInterference(const LiveInterval & VirtReg,MCRegister PhysReg,const SmallVirtRegSet & FixedRegisters) const canEvictHintInterference() argument
186 canEvictInterferenceBasedOnCost(const LiveInterval & VirtReg,MCRegister PhysReg,bool IsHint,EvictionCost & MaxCost,const SmallVirtRegSet & FixedRegisters) const canEvictInterferenceBasedOnCost() argument
276 tryFindEvictionCandidate(const LiveInterval & VirtReg,const AllocationOrder & Order,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) const tryFindEvictionCandidate() argument
[all...]
H A DLiveIntervalUnion.cpp28 void LiveIntervalUnion::unify(const LiveInterval &VirtReg, in unify()
56 void LiveIntervalUnion::extract(const LiveInterval &VirtReg, in extract()
H A DAllocationOrder.cpp29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create() argument
H A DRegisterCoalescer.h64 CoalescerPair(Register VirtReg, MCRegister PhysReg, in CoalescerPair()
H A DRegAllocBase.cpp88 while (const LiveInterval *VirtReg = dequeue()) { allocatePhysRegs() local
[all...]
H A DVirtRegMap.cpp342 Register VirtReg = Register::index2VirtReg(Idx); in addMBBLiveIns() local
552 Register VirtReg in rewrite() local
[all...]
H A DPHIElimination.cpp164 Register VirtReg = Register::index2VirtReg(Index); runOnMachineFunction() local
250 isImplicitlyDefined(unsigned VirtReg,const MachineRegisterInfo & MRI) isImplicitlyDefined() argument
H A DMLRegAllocEvictAdvisor.cpp335 canEvictHintInterference(const LiveInterval & VirtReg,MCRegister PhysReg,const SmallVirtRegSet & FixedRegisters) const canEvictHintInterference() argument
597 loadInterferenceFeatures(const LiveInterval & VirtReg,MCRegister PhysReg,bool IsHint,const SmallVirtRegSet & FixedRegisters,llvm::SmallVectorImpl<float> & Largest,size_t Pos,llvm::SmallVectorImpl<LRStartEndInfo> & LRPosInfo) const loadInterferenceFeatures() argument
664 tryFindEvictionCandidate(const LiveInterval & VirtReg,const AllocationOrder & Order,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) const tryFindEvictionCandidate() argument
1085 tryFindEvictionCandidatePosition(const LiveInterval & VirtReg,const AllocationOrder & Order,unsigned OrderLimit,uint8_t CostPerUseLimit,const SmallVirtRegSet & FixedRegisters) const tryFindEvictionCandidatePosition() argument
[all...]
H A DRegAllocGreedy.h86 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage() argument
95 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
[all...]
H A DLiveDebugVariables.cpp788 void LDVImpl::mapVirtReg(Register VirtReg, UserValue *EC) { in mapVirtReg() argument
794 UserValue *LDVImpl::lookupVirtReg(Register VirtReg) { in lookupVirtReg() argument
1531 Register VirtReg = Loc.getReg(); in rewriteLocations() local
[all...]
H A DMachineBasicBlock.cpp660 if (!MRI.constrainRegClass(VirtReg, RC)) in addLiveIn() local
653 Register VirtReg = I->getOperand(0).getReg(); addLiveIn() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastPreTileConfig.cpp118 int X86FastPreTileConfig::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor() argument
139 mayLiveOut(Register VirtReg,MachineInstr * CfgMI) mayLiveOut() argument
202 spill(MachineBasicBlock::iterator Before,Register VirtReg,bool Kill) spill() argument
669 Register VirtReg = Register::index2VirtReg(I); runOnMachineFunction() local
[all...]
H A DX86TileConfig.cpp121 Register VirtReg = Register::index2VirtReg(I); INITIALIZE_PASS_DEPENDENCY() local
H A DX86RegisterInfo.cpp1068 VRM->assignVirt2Shape(VirtReg, Shape); in getRegAllocationHints() argument
1030 getTileShape(Register VirtReg,VirtRegMap * VRM,const MachineRegisterInfo * MRI) getTileShape() argument
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp125 const Register VirtReg = MO.getReg(); in rewriteRegs() local
/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DVirtRegMap.h169 Register getOriginal(Register VirtReg) const { in getOriginal()
H A DScheduleDAGInstrs.h54 unsigned VirtReg; global() member
H A DRegisterPressure.h536 bool hasUntiedDef(Register VirtReg) const { in hasUntiedDef()
H A DTargetRegisterInfo.h1112 shouldUseLastChanceRecoloringForVirtReg(const MachineFunction & MF,const LiveInterval & VirtReg) shouldUseLastChanceRecoloringForVirtReg() argument
1127 shouldUseDeferredSpillingForVirtReg(const MachineFunction & MF,const LiveInterval & VirtReg) shouldUseDeferredSpillingForVirtReg() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp752 getRegAllocationHints(Register VirtReg,ArrayRef<MCPhysReg> Order,SmallVectorImpl<MCPhysReg> & Hints,const MachineFunction & MF,const VirtRegMap * VRM,const LiveRegMatrix * Matrix) const getRegAllocationHints() argument

12