Lines Matching defs:VirtReg
234 bool RAGreedy::LRE_CanEraseVirtReg(Register VirtReg) {
235 LiveInterval &LI = LIS->getInterval(VirtReg);
236 if (VRM->hasPhys(VirtReg)) {
244 // dump will show the right state for that VirtReg.
249 void RAGreedy::LRE_WillShrinkVirtReg(Register VirtReg) {
250 if (!VRM->hasPhys(VirtReg))
254 LiveInterval &LI = LIS->getInterval(VirtReg);
396 /// tryAssign - Try to assign VirtReg to an available register.
397 MCRegister RAGreedy::tryAssign(const LiveInterval &VirtReg,
404 if (!Matrix->checkInterference(VirtReg, *I)) {
418 if (Register Hint = MRI->getSimpleHint(VirtReg.reg()))
423 if (EvictAdvisor->canEvictHintInterference(VirtReg, PhysHint,
425 evictInterference(VirtReg, PhysHint, NewVRegs);
430 if (trySplitAroundHintReg(PhysHint, VirtReg, NewVRegs, Order))
435 SetOfBrokenHints.insert(&VirtReg);
447 MCRegister CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters);
455 bool RegAllocEvictionAdvisor::canReassign(const LiveInterval &VirtReg,
459 LiveIntervalUnion::Query SubQ(VirtReg, Matrix->getLiveUnions()[Unit]);
464 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix)) {
469 LLVM_DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
478 /// evictInterference - Evict any interferring registers that prevent VirtReg
481 void RAGreedy::evictInterference(const LiveInterval &VirtReg,
484 // Make sure that VirtReg has a cascade number, and assign that cascade
487 unsigned Cascade = ExtraInfo->getOrAssignNewCascade(VirtReg.reg());
495 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
506 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
512 VirtReg.isSpillable() < Intf->isSpillable()) &&
531 RegAllocEvictionAdvisor::getOrderLimit(const LiveInterval &VirtReg,
538 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg());
574 /// @param VirtReg Currently unassigned virtual register.
576 /// @return Physreg to assign VirtReg, or 0.
577 MCRegister RAGreedy::tryEvict(const LiveInterval &VirtReg,
586 VirtReg, Order, CostPerUseLimit, FixedRegisters);
588 evictInterference(VirtReg, BestPhys, NewVRegs);
1060 MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg,
1063 if (!TRI->shouldRegionSplitForVirtReg(*MF, VirtReg))
1083 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
1090 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs);
1171 unsigned RAGreedy::calculateRegionSplitCost(const LiveInterval &VirtReg,
1189 unsigned RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
1194 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1229 // VirtReg has a physical Hint, this function tries to split VirtReg around
1232 const LiveInterval &VirtReg,
1235 // Split the VirtReg may generate COPY instructions in multiple cold basic
1242 if (ExtraInfo->getStage(VirtReg) >= RS_Split2)
1246 Register Reg = VirtReg.reg();
1248 // Compute the cost of assigning a non Hint physical register to VirtReg.
1259 // Check if VirtReg interferes with OtherReg after this COPY instruction.
1260 if (VirtReg.liveAt(LIS->getInstructionIndex(Instr).getRegSlot()))
1277 SA->analyze(&VirtReg);
1282 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
1293 unsigned RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
1296 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1297 Register Reg = VirtReg.reg();
1299 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1380 /// VirtReg.
1382 const MachineInstr *MI, const LiveInterval &VirtReg,
1394 LaneBitmask ReadMask = getInstReadLaneMask(MRI, *TRI, *MI, VirtReg.reg());
1397 for (const LiveInterval::SubRange &S : VirtReg.subranges()) {
1414 unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
1417 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg());
1422 if (!VirtReg.hasSubRanges())
1429 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1452 getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC,
1455 (!SplitSubClass && VirtReg.hasSubRanges() &&
1456 !readsLaneSubset(*MRI, MI, VirtReg, TRI, Use, TII))) {
1474 DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS);
1510 // We know that VirtReg is a continuous interval from FirstInstr to
1564 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
1567 unsigned RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
1596 // If VirtReg is live across any register mask operands, compute a list of
1599 if (Matrix->checkRegMaskInterference(VirtReg)) {
1603 // Constrain to VirtReg's live range.
1645 bool ProgressRequired = ExtraInfo->getStage(VirtReg) >= RS_Split2;
1664 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1760 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1769 DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS);
1795 /// trySplit - Try to split VirtReg or one of its interferences, making it
1797 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1798 unsigned RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order,
1802 if (ExtraInfo->getStage(VirtReg) >= RS_Spill)
1806 if (LIS->intervalIsInOneMBB(VirtReg)) {
1809 SA->analyze(&VirtReg);
1810 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1813 return tryInstructionSplit(VirtReg, Order, NewVRegs);
1819 SA->analyze(&VirtReg);
1824 if (ExtraInfo->getStage(VirtReg) < RS_Split2) {
1825 MCRegister PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1831 return tryBlockSplit(VirtReg, Order, NewVRegs);
1860 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1864 /// for \p VirtReg.
1868 MCRegister PhysReg, const LiveInterval &VirtReg,
1870 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg());
1873 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit);
1884 // If Intf is done and sits on the same register class as VirtReg, it
1886 // VirtReg. However there are at least two exceptions.
1888 // If VirtReg has tied defs and Intf doesn't, then
1898 !(hasTiedDef(MRI, VirtReg.reg()) &&
1911 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
1913 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
1942 /// \p Order defines the preferred allocation order for \p VirtReg.
1952 /// \return a physical register that can be used for VirtReg or ~0u if none
1954 unsigned RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
1960 if (!TRI->shouldUseLastChanceRecoloringForVirtReg(*MF, VirtReg))
1963 LLVM_DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
1968 assert((ExtraInfo->getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
1983 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
1985 assert(!FixedRegisters.count(VirtReg.reg()));
1986 FixedRegisters.insert(VirtReg.reg());
1991 LLVM_DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
1997 if (Matrix->checkInterference(VirtReg, PhysReg) >
2007 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2014 // with VirtReg on PhysReg (or one of its aliases). Enqueue them for
2030 // Do as if VirtReg was assigned to PhysReg so that the underlying
2033 Matrix->assign(VirtReg, PhysReg);
2045 // I.e., VirtReg must be unassigned.
2046 Matrix->unassign(VirtReg);
2050 LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2055 Matrix->unassign(VirtReg);
2142 MCRegister RAGreedy::selectOrSplit(const LiveInterval &VirtReg,
2149 selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters, RecolorStack);
2175 const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
2177 if (ExtraInfo->getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
2180 SA->analyze(&VirtReg);
2189 if (ExtraInfo->getStage(VirtReg) < RS_Split) {
2192 SA->analyze(&VirtReg);
2195 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
2202 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
2275 /// Using the register assigned to \p VirtReg, try to recolor
2276 /// all the live ranges that are copy-related with \p VirtReg.
2283 void RAGreedy::tryHintRecoloring(const LiveInterval &VirtReg) {
2290 Register Reg = VirtReg.reg();
2408 MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
2416 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix);
2418 tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) {
2424 MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2433 // Non emtpy NewVRegs means VirtReg has been split.
2437 LiveRangeStage Stage = ExtraInfo->getStage(VirtReg);
2439 << ExtraInfo->getCascade(VirtReg.reg()) << '\n');
2446 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit,
2448 Register Hint = MRI->getSimpleHint(VirtReg.reg());
2449 // If VirtReg has a hint and that hint is broken record this
2455 SetOfBrokenHints.insert(&VirtReg);
2465 ExtraInfo->setStage(VirtReg, RS_Split);
2467 NewVRegs.push_back(VirtReg.reg());
2472 // Try splitting VirtReg or interferences.
2474 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
2481 if (Stage >= RS_Done || !VirtReg.isSpillable()) {
2482 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
2486 // Finally spill VirtReg itself.
2488 TRI->shouldUseDeferredSpillingForVirtReg(*MF, VirtReg)) &&
2489 ExtraInfo->getStage(VirtReg) < RS_Memory) {
2494 ExtraInfo->setStage(VirtReg, RS_Memory);
2496 NewVRegs.push_back(VirtReg.reg());
2500 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2507 DebugVars->splitRegister(VirtReg.reg(), LRE.regs(), *LIS);