Lines Matching defs:VirtReg
202 Register VirtReg; ///< Virtual register number.
208 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {}
211 return Register::virtReg2Index(VirtReg);
351 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) {
352 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
355 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const {
356 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
363 void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
366 Register VirtReg);
367 bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
369 bool useVirtReg(MachineInstr &MI, MachineOperand &MO, Register VirtReg);
378 Register traceCopies(Register VirtReg) const;
382 int getStackSpaceFor(Register VirtReg);
383 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
385 void reload(MachineBasicBlock::iterator Before, Register VirtReg,
388 bool mayLiveOut(Register VirtReg);
389 bool mayLiveIn(Register VirtReg);
464 int RegAllocFastImpl::getStackSpaceFor(Register VirtReg) {
466 int SS = StackSlotForVirtReg[VirtReg];
472 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
478 StackSlotForVirtReg[VirtReg] = FrameIdx;
491 /// Returns false if \p VirtReg is known to not live out of the current block.
492 bool RegAllocFastImpl::mayLiveOut(Register VirtReg) {
493 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) {
504 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
506 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
514 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
523 for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) {
525 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
535 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
544 /// Returns false if \p VirtReg is known to not be live into the current block.
545 bool RegAllocFastImpl::mayLiveIn(Register VirtReg) {
546 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg)))
552 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
554 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
563 /// DBG_VALUEs with \p VirtReg operands with the stack slot.
565 Register VirtReg, MCPhysReg AssignedReg, bool Kill,
567 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in "
569 int FI = getStackSpaceFor(VirtReg);
572 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
574 VirtReg);
582 SmallVectorImpl<MachineOperand *> &LRIDbgOperands = LiveDbgValueMap[VirtReg];
626 Register VirtReg, MCPhysReg PhysReg) {
627 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into "
629 int FI = getStackSpaceFor(VirtReg);
630 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
631 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg);
699 reload(MBB.begin(), LR.VirtReg, PhysReg);
701 reload(InsertBefore, LR.VirtReg, PhysReg);
730 switch (unsigned VirtReg = RegUnitStates[Unit]) {
732 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
736 reload(ReloadBefore, VirtReg, LRI->PhysReg);
759 switch (unsigned VirtReg = RegUnitStates[FirstUnit]) {
768 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
770 LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n');
784 switch (unsigned VirtReg = RegUnitStates[Unit]) {
792 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 ||
793 findLiveVirtReg(VirtReg)->LiveOut;
802 Register VirtReg,
804 auto UDBGValIter = DanglingDbgValues.find(VirtReg);
811 if (!DbgValue->hasDebugOperandForReg(VirtReg))
827 for (MachineOperand &MO : DbgValue->getDebugOperandsForReg(VirtReg)) {
837 /// proper container for VirtReg now. The physical register must not be used
841 Register VirtReg = LR.VirtReg;
842 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to "
847 setPhysRegState(PhysReg, VirtReg);
849 assignDanglingDebugValues(AtMI, VirtReg, PhysReg);
870 /// Check if any of \p VirtReg's definitions is a copy. If it is follow the
873 Register RegAllocFastImpl::traceCopies(Register VirtReg) const {
876 for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) {
890 /// Allocates a physical register for VirtReg.
893 const Register VirtReg = LR.VirtReg;
896 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
897 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg)
919 Register Hint1 = traceCopies(VirtReg);
982 Register VirtReg = MO.getReg();
983 assert(VirtReg.isVirtual() && "Expected virtreg");
984 if (!shouldAllocateRegister(VirtReg))
987 LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
992 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
1012 Register VirtReg) {
1013 if (!shouldAllocateRegister(VirtReg))
1015 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
1037 return defineVirtReg(MI, OpNum, VirtReg, true);
1040 /// Allocates a register for VirtReg definition. Typically the register is
1048 Register VirtReg, bool LookAtPhysRegUses) {
1049 assert(VirtReg.isVirtual() && "Not a virtual register");
1050 if (!shouldAllocateRegister(VirtReg))
1055 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1058 if (mayLiveOut(VirtReg)) {
1071 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
1080 LLVM_DEBUG(dbgs() << "In def of " << printReg(VirtReg, TRI)
1093 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
1098 int FI = StackSlotForVirtReg[VirtReg];
1099 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
1104 &RC, TRI, VirtReg);
1117 BundleVirtRegsMap[VirtReg] = PhysReg;
1123 /// Allocates a register for a VirtReg use.
1126 Register VirtReg) {
1127 assert(VirtReg.isVirtual() && "Not a virtual register");
1128 if (!shouldAllocateRegister(VirtReg))
1132 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1135 if (mayLiveOut(VirtReg)) {
1162 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
1173 BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1224 switch (unsigned VirtReg = RegUnitStates[Unit]) {
1233 dbgs() << ' ' << printRegUnit(Unit, TRI) << '=' << printReg(VirtReg);
1234 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
1252 Register VirtReg = LR.VirtReg;
1253 assert(VirtReg.isVirtual() && "Bad map key");
1258 assert(RegUnitStates[Unit] == VirtReg && "inverse map valid");