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Searched defs:VT (Results 1 – 25 of 281) sorted by relevance

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/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DMatchContext.h41 return TLI.isOperationLegal(Op, VT); in isOperationLegal() argument
111 // DAG.getNode(Opcode, DL, VT); } in getNode() argument
119 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2) getNode() argument
127 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3) getNode() argument
136 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue Operand,SDNodeFlags Flags) getNode() argument
145 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDNodeFlags Flags) getNode() argument
154 getNode(unsigned Opcode,const SDLoc & DL,EVT VT,SDValue N1,SDValue N2,SDValue N3,SDNodeFlags Flags) getNode() argument
163 isOperationLegal(unsigned Op,EVT VT) isOperationLegal() argument
[all...]
H A DLegalizeVectorOps.cpp702 MVT VT = Node->getSimpleValueType(0); Promote() local
743 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); PromoteINT_TO_FP() local
781 MVT VT = Node->getSimpleValueType(0); PromoteFP_TO_INT() local
1137 EVT VT = Node->getValueType(0); ExpandSELECT() local
1190 EVT VT = Node->getValueType(0); ExpandSEXTINREG() local
1212 EVT VT = Node->getValueType(0); ExpandANY_EXTEND_VECTOR_INREG() local
1247 EVT VT = Node->getValueType(0); ExpandSIGN_EXTEND_VECTOR_INREG() local
1271 EVT VT = Node->getValueType(0); ExpandZERO_EXTEND_VECTOR_INREG() local
1305 createBSWAPShuffleMask(EVT VT,SmallVectorImpl<int> & ShuffleMask) createBSWAPShuffleMask() argument
1313 EVT VT = Node->getValueType(0); ExpandBSWAP() local
1346 EVT VT = Node->getValueType(0); ExpandBITREVERSE() local
1411 EVT VT = Mask.getValueType(); ExpandVSELECT() local
1462 EVT VT = Mask.getValueType(); ExpandVP_SELECT() local
1526 EVT VT = Node->getValueType(0); ExpandVP_REM() local
1573 EVT VT = Src.getValueType(); ExpandUINT_TO_FLOAT() local
1675 EVT VT = Node->getValueType(0); ExpandFSUB() local
1751 EVT VT = Node->getValueType(0); ExpandSETCC() local
1846 EVT VT = Node->getValueType(0); tryExpandVecMathCall() local
1942 EVT VT = Node->getValueType(0); UnrollStrictFPOp() local
2001 EVT VT = Node->getValueType(0); UnrollVSETCC() local
[all...]
H A DResourcePriorityQueue.cpp93 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
131 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
326 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
335 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
474 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
485 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
H A DLegalizeTypes.h62 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { in getTypeAction() argument
67 bool isTypeLegal(EVT VT) const { in isTypeLegal() argument
72 bool isSimpleLegalType(EVT VT) const { in isSimpleLegalType() argument
76 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType() argument
282 EVT VT = Op.getValueType(); VPSExtPromotedInteger() local
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/llvm-project/llvm/utils/TableGen/
H A DVTEmitter.cpp
/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h261 SimpleValueType VT = EltTyTable[SimpleTy - FIRST_VALUETYPE]; getVectorElementType() local
371 knownBitsGT(MVT VT) knownBitsGT() argument
377 knownBitsGE(MVT VT) knownBitsGE() argument
382 knownBitsLT(MVT VT) knownBitsLT() argument
388 knownBitsLE(MVT VT) knownBitsLE() argument
393 bitsGT(MVT VT) bitsGT() argument
400 bitsGE(MVT VT) bitsGE() argument
407 bitsLT(MVT VT) bitsLT() argument
414 bitsLE(MVT VT) bitsLE() argument
440 getVectorVT(MVT VT,unsigned NumElements) getVectorVT() argument
450 getScalableVectorVT(MVT VT,unsigned NumElements) getScalableVectorVT() argument
460 getVectorVT(MVT VT,unsigned NumElements,bool IsScalable) getVectorVT() argument
466 getVectorVT(MVT VT,ElementCount EC) getVectorVT() argument
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/llvm-project/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.class/unique.ptr.ctor/
H A Dmove.pass.cpp62 TEST_CONSTEXPR_CXX23 void sink2(std::unique_ptr<VT, Deleter<VT> > p) { in sink2()
68 void sink3(std::unique_ptr<VT, NCDeleter<VT>&> p) { in sink3()
85 typedef typename std::conditional<!IsArray, A, A[]>::type VT; in test_basic() typedef
186 typedef typename std::conditional<!IsArray, A, A[]>::type VT; in test_sink3() typedef
H A Dpointer_deleter.pass.cpp57 typedef typename std::conditional<!IsArray, int, int[]>::type VT; in test_sfinae() typedef
107 typedef typename std::conditional<!IsArray, int, int[]>::type VT; in test_noexcept() typedef
208 typedef typename std::conditional<!IsArray, A, A[]>::type VT; in test_basic() typedef
310 typedef typename std::conditional<!IsArray, A, A[]>::type VT; in test_nullptr() typedef
/llvm-project/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.class/unique.ptr.modifiers/
H A Dreset.pass.cpp23 typedef typename std::conditional<IsArray, A[], A>::type VT; in test_reset_pointer() typedef
69 typedef typename std::conditional<IsArray, A[], A>::type VT; in test_reset_nullptr() typedef
96 typedef typename std::conditional<IsArray, A[], A>::type VT; in test_reset_no_arg() typedef
/llvm-project/libcxx/test/std/iterators/iterator.primitives/iterator.traits/
H A Dempty.verify.cpp
/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp49 unsigned NumRegs = TLI.getNumRegisters(Ctx, VT); in computeLegalValueVTs() local
128 Params.push_back(EVT(VT).getEVTString()); in WebAssemblyFunctionInfo() local
130 Results.push_back(EVT(VT).getEVTString()); in WebAssemblyFunctionInfo() local
159 addParam(WebAssembly::parseMVT(VT.Value)); in initializeBaseYamlFields() local
161 for (auto VT : YamlMFI.Results) initializeBaseYamlFields() local
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H A DWebAssemblyMachineFunctionInfo.h81 void addParam(MVT VT) { Params.push_back(VT); } in addParam()
84 void addResult(MVT VT) { Results.push_back(VT); } in addResult()
93 void setLocal(size_t i, MVT VT) { Locals[i] = VT; } in setLocal()
94 void addLocal(MVT VT) { Locals.push_back(VT); } in addLocal()
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h478 virtual bool shouldExpandCttzElements(EVT VT) const { return true; } in shouldReassociateReduction() argument
457 shouldExpandGetActiveLaneMask(EVT VT,EVT OpVT) shouldExpandGetActiveLaneMask() argument
468 shouldExpandCttzElements(EVT VT) shouldExpandCttzElements() argument
500 getPreferredVectorAction(MVT VT) getPreferredVectorAction() argument
542 isIntDivCheap(EVT VT,AttributeList Attr) isIntDivCheap() argument
545 hasStandaloneRem(EVT VT) hasStandaloneRem() argument
705 isCtpopFast(EVT VT) isCtpopFast() argument
711 getCustomCtpopCost(EVT VT,ISD::CondCode Cond) getCustomCtpopCost() argument
755 convertSetCCLogicToBitwiseLogic(EVT VT) convertSetCCLogicToBitwiseLogic() argument
764 MVT VT = MVT::getIntegerVT(NumBits); hasFastEqualityCompare() local
893 preferedOpcodeForCmpEqPiecesOfOperand(EVT VT,unsigned ShiftOpc,bool MayTransformRotate,const APInt & ShiftOrRotateAmt,const std::optional<APInt> & AndMask) preferedOpcodeForCmpEqPiecesOfOperand() argument
904 preferIncOfAddToSubOfNot(EVT VT) preferIncOfAddToSubOfNot() argument
911 preferABDSToABSWithNSW(EVT VT) preferABDSToABSWithNSW() argument
922 preferSextInRegOfTruncate(EVT TruncVT,EVT VT,EVT ExtVT) preferSextInRegOfTruncate() argument
957 enableAggressiveFMAFusion(EVT VT) enableAggressiveFMAFusion() argument
1047 getRepRegClassFor(MVT VT) getRepRegClassFor() argument
1054 getRepRegClassCostFor(MVT VT) getRepRegClassCostFor() argument
1076 isTypeLegal(EVT VT) isTypeLegal() argument
1093 getTypeAction(MVT VT) getTypeAction() argument
1097 setTypeAction(MVT VT,LegalizeTypeAction Action) setTypeAction() argument
1126 getTypeAction(LLVMContext & Context,EVT VT) getTypeAction() argument
1129 getTypeAction(MVT VT) getTypeAction() argument
1139 getTypeToTransformTo(LLVMContext & Context,EVT VT) getTypeToTransformTo() argument
1147 getTypeToExpandTo(LLVMContext & Context,EVT VT) getTypeToExpandTo() argument
1179 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) getVectorTypeBreakdownForCallingConv() argument
1253 getOperationAction(unsigned Op,EVT VT) getOperationAction() argument
1266 isSupportedFixedPointOperation(unsigned Op,EVT VT,unsigned Scale) isSupportedFixedPointOperation() argument
1275 getFixedPointOperationAction(unsigned Op,EVT VT,unsigned Scale) getFixedPointOperationAction() argument
1304 getStrictFPOperationAction(unsigned Op,EVT VT) getStrictFPOperationAction() argument
1363 isOperationCustom(unsigned Op,EVT VT) isOperationCustom() argument
1425 isOperationExpand(unsigned Op,EVT VT) isOperationExpand() argument
1430 isOperationLegal(unsigned Op,EVT VT) isOperationLegal() argument
1520 getIndexedLoadAction(unsigned IdxMode,MVT VT) getIndexedLoadAction() argument
1525 isIndexedLoadLegal(unsigned IdxMode,EVT VT) isIndexedLoadLegal() argument
1534 getIndexedStoreAction(unsigned IdxMode,MVT VT) getIndexedStoreAction() argument
1539 isIndexedStoreLegal(unsigned IdxMode,EVT VT) isIndexedStoreLegal() argument
1548 getIndexedMaskedLoadAction(unsigned IdxMode,MVT VT) getIndexedMaskedLoadAction() argument
1553 isIndexedMaskedLoadLegal(unsigned IdxMode,EVT VT) isIndexedMaskedLoadLegal() argument
1562 getIndexedMaskedStoreAction(unsigned IdxMode,MVT VT) getIndexedMaskedStoreAction() argument
1567 isIndexedMaskedStoreLegal(unsigned IdxMode,EVT VT) isIndexedMaskedStoreLegal() argument
1575 shouldExtendGSIndex(EVT VT,EVT & EltTy) shouldExtendGSIndex() argument
1599 getCondCodeAction(ISD::CondCode CC,MVT VT) getCondCodeAction() argument
1612 isCondCodeLegal(ISD::CondCode CC,MVT VT) isCondCodeLegal() argument
1618 isCondCodeLegalOrCustom(ISD::CondCode CC,MVT VT) isCondCodeLegalOrCustom() argument
1625 getTypeToPromoteTo(unsigned Op,MVT VT) getTypeToPromoteTo() argument
1710 getRegisterType(MVT VT) getRegisterType() argument
1716 getRegisterType(LLVMContext & Context,EVT VT) getRegisterType() argument
1770 getRegisterTypeForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT) getRegisterTypeForCallingConv() argument
1779 getNumRegistersForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT) getNumRegistersForCallingConv() argument
1814 isPaddedAtMostSignificantBitsWhenStored(EVT VT) isPaddedAtMostSignificantBitsWhenStored() argument
1821 hasBigEndianPartOrdering(EVT VT,const DataLayout & DL) hasBigEndianPartOrdering() argument
2378 shouldNormalizeToSelectSequence(LLVMContext & Context,EVT VT) shouldNormalizeToSelectSequence() argument
2390 isProfitableToCombineMinNumMaxNum(EVT VT) isProfitableToCombineMinNumMaxNum() argument
2395 convertSelectOfConstantsToMath(EVT VT) convertSelectOfConstantsToMath() argument
2405 decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C) decomposeMulByConstant() argument
2518 addRegisterClass(MVT VT,const TargetRegisterClass * RC) addRegisterClass() argument
2535 setOperationAction(unsigned Op,MVT VT,LegalizeAction Action) setOperationAction() argument
2539 setOperationAction(ArrayRef<unsigned> Ops,MVT VT,LegalizeAction Action) setOperationAction() argument
2546 for (auto VT : VTs) setOperationAction() local
2608 setIndexedLoadAction(ArrayRef<unsigned> IdxModes,MVT VT,LegalizeAction Action) setIndexedLoadAction() argument
2616 for (auto VT : VTs) setIndexedLoadAction() local
2625 setIndexedStoreAction(ArrayRef<unsigned> IdxModes,MVT VT,LegalizeAction Action) setIndexedStoreAction() argument
2633 for (auto VT : VTs) setIndexedStoreAction() local
2642 setIndexedMaskedLoadAction(unsigned IdxMode,MVT VT,LegalizeAction Action) setIndexedMaskedLoadAction() argument
2652 setIndexedMaskedStoreAction(unsigned IdxMode,MVT VT,LegalizeAction Action) setIndexedMaskedStoreAction() argument
2659 setCondCodeAction(ArrayRef<ISD::CondCode> CCs,MVT VT,LegalizeAction Action) setCondCodeAction() argument
2675 for (auto VT : VTs) setCondCodeAction() local
3016 EVT VT = getValueType(DL, Ext->getType()); isExtLoad() local
3206 isFNegFree(EVT VT) isFNegFree() argument
3213 isFAbsFree(EVT VT) isFAbsFree() argument
3284 generateFMAsInMachineCombiner(EVT VT,CodeGenOptLevel OptLevel) generateFMAsInMachineCombiner() argument
3300 shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,EVT VT) shouldFoldSelectWithIdentityConstant() argument
3333 isExtractVecEltCheap(EVT VT,unsigned Index) isExtractVecEltCheap() argument
3341 shouldFormOverflowOp(unsigned Opcode,EVT VT,bool MathUsed) shouldFormOverflowOp() argument
3371 shouldAvoidTransformToShift(EVT VT,unsigned Amount) shouldAvoidTransformToShift() argument
3377 shouldFoldSelectWithSingleBitTest(EVT VT,const APInt & AndMask) shouldFoldSelectWithSingleBitTest() argument
3389 shouldConvertFpToSat(unsigned Op,EVT FPVT,EVT VT) shouldConvertFpToSat() argument
3651 setIndexedModeAction(unsigned IdxMode,MVT VT,unsigned Shift,LegalizeAction Action) setIndexedModeAction() argument
3660 getIndexedModeAction(unsigned IdxMode,MVT VT,unsigned Shift) getIndexedModeAction() argument
4347 isTypeDesirableForOp(unsigned,EVT VT) isTypeDesirableForOp() argument
4811 getTypeForExtReturn(LLVMContext & Context,EVT VT,ISD::NodeType) getTypeForExtReturn() argument
[all...]
/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp229 VT.getVectorNumElements() / 2); in scaleVectorType() argument
257 assert(VT.getSizeInBits() >= 256 && in genShuffleBland() argument
287 reorderSubVector(MVT VT,SmallVectorImpl<Value * > & TransposedMatrix,ArrayRef<Value * > Vec,ArrayRef<int> VPShuf,unsigned VecElems,unsigned Stride,IRBuilder<> & Builder) reorderSubVector() argument
327 MVT VT = MVT::v8i16; interleave8bitStride4VF8() local
367 MVT VT = MVT::getVectorVT(MVT::i8, NumOfElm); interleave8bitStride4() local
436 createShuffleStride(MVT VT,int Stride,SmallVectorImpl<int> & Mask) createShuffleStride() argument
450 setGroupSize(MVT VT,SmallVectorImpl<int> & SizeInfo) setGroupSize() argument
473 DecodePALIGNRMask(MVT VT,unsigned Imm,SmallVectorImpl<int> & ShuffleMask,bool AlignDirection=true,bool Unary=false) DecodePALIGNRMask() argument
558 MVT VT = MVT::getVT(Shuffles[0]->getType()); deinterleave8bitStride3() local
606 group2Shuffle(MVT VT,SmallVectorImpl<int> & Mask,SmallVectorImpl<int> & Output) group2Shuffle() argument
641 MVT VT = MVT::getVectorVT(MVT::i8, VecElems); interleave8bitStride3() local
[all...]
/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp297 getFPLibCall(EVT VT,RTLIB::Libcall Call_F32,RTLIB::Libcall Call_F64,RTLIB::Libcall Call_F80,RTLIB::Libcall Call_F128,RTLIB::Libcall Call_PPCF128) getFPLibCall() argument
641 getOUTLINE_ATOMIC(unsigned Opc,AtomicOrdering Order,MVT VT) getOUTLINE_ATOMIC() argument
682 getSYNC(unsigned Opc,MVT VT) getSYNC() argument
885 for (MVT VT : MVT::fp_valuetypes()) { initActions() local
894 for (MVT VT : MVT::all_valuetypes()) { initActions() local
1252 getVectorTypeBreakdownMVT(MVT VT,MVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT,TargetLoweringBase * TLI) getVectorTypeBreakdownMVT() argument
1568 MVT VT = (MVT::SimpleValueType) i; computeRegisterProperties() local
1707 getVectorTypeBreakdown(LLVMContext & Context,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const getVectorTypeBreakdown() argument
1837 EVT VT = ValueVTs[j]; GetReturnInfo() local
1886 allowsMemoryAccessForAlignment(LLVMContext & Context,const DataLayout & DL,EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMemoryAccessForAlignment() argument
1906 allowsMemoryAccessForAlignment(LLVMContext & Context,const DataLayout & DL,EVT VT,const MachineMemOperand & MMO,unsigned * Fast) const allowsMemoryAccessForAlignment() argument
1913 allowsMemoryAccess(LLVMContext & Context,const DataLayout & DL,EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMemoryAccess() argument
1922 allowsMemoryAccess(LLVMContext & Context,const DataLayout & DL,EVT VT,const MachineMemOperand & MMO,unsigned * Fast) const allowsMemoryAccess() argument
1933 EVT VT = getApproximateEVTForLLT(Ty, DL, Context); allowsMemoryAccess() local
2210 getReciprocalOpName(bool IsSqrt,EVT VT) getReciprocalOpName() argument
2255 getOpEnabled(bool IsSqrt,EVT VT,StringRef Override) getOpEnabled() argument
2315 getOpRefinementSteps(bool IsSqrt,EVT VT,StringRef Override) getOpRefinementSteps() argument
2361 getRecipEstimateSqrtEnabled(EVT VT,MachineFunction & MF) const getRecipEstimateSqrtEnabled() argument
2366 getRecipEstimateDivEnabled(EVT VT,MachineFunction & MF) const getRecipEstimateDivEnabled() argument
2371 getSqrtRefinementSteps(EVT VT,MachineFunction & MF) const getSqrtRefinementSteps() argument
2376 getDivRefinementSteps(EVT VT,MachineFunction & MF) const getDivRefinementSteps() argument
[all...]
H A DCallingConvLower.cpp103 MVT VT = Outs[i].VT; in CheckReturn() local
117 MVT VT = Outs[i].VT; in AnalyzeReturn() local
165 MVT VT = Ins[i].VT; AnalyzeCallResult() local
178 AnalyzeCallResult(MVT VT,CCAssignFn Fn) AnalyzeCallResult() argument
193 isValueTypeInRegForCC(CallingConv::ID CC,MVT VT) isValueTypeInRegForCC() argument
202 getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> & Regs,MVT VT,CCAssignFn Fn) getRemainingRegParmsForType() argument
[all...]
H A DValueTypes.cpp39 EVT VT; getExtendedIntegerVT() local
45 getExtendedVectorVT(LLVMContext & Context,EVT VT,unsigned NumElements,bool IsScalable) getExtendedVectorVT() argument
54 getExtendedVectorVT(LLVMContext & Context,EVT VT,ElementCount EC) getExtendedVectorVT() argument
/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DNumericalStabilitySanitizer.cpp268 Twine(ClShadowMapping[VT])); in MappingConfig() local
231 typeFromFTValueType(FTValueType VT,LLVMContext & Context) typeFromFTValueType() argument
246 typeNameFromFTValueType(FTValueType VT) typeNameFromFTValueType() argument
312 if (const auto VT = ftValueTypeFromType(FT)) getExtendedFPType() local
340 if (const auto VT = ftValueTypeFromType(FT)) getMemoryExtentsOrDie() local
612 const FTValueType VT = static_cast<FTValueType>(I); NumericalStabilitySanitizer() local
716 Type *VT = Arg.getType(); createShadowArguments() local
815 Type *VT = Arg->getType(); populateShadowStack() local
848 if (const auto VT = ftValueTypeFromType(Ty)) emitCheckInternal() local
1049 Type *VT = Phi.getType(); maybeCreateShadowPhi() local
1061 handleLoad(LoadInst & Load,Type * VT,Type * ExtendedVT) handleLoad() argument
1137 handleTrunc(const FPTruncInst & Trunc,Type * VT,Type * ExtendedVT,const ValueToShadowMap & Map,IRBuilder<> & Builder) handleTrunc() argument
1184 handleExt(const FPExtInst & Ext,Type * VT,Type * ExtendedVT,const ValueToShadowMap & Map,IRBuilder<> & Builder) handleExt() argument
1481 getIntrinsicFromLibfunc(Function & Fn,Type * VT,const TargetLibraryInfo & TLI) getIntrinsicFromLibfunc() argument
1496 maybeHandleKnownCallBase(CallBase & Call,Type * VT,Type * ExtendedVT,const TargetLibraryInfo & TLI,const ValueToShadowMap & Map,IRBuilder<> & Builder) maybeHandleKnownCallBase() argument
1570 handleCallBase(CallBase & Call,Type * VT,Type * ExtendedVT,const TargetLibraryInfo & TLI,const ValueToShadowMap & Map,IRBuilder<> & Builder) handleCallBase() argument
1608 Type *VT = Inst.getType(); createShadowValueWithOperandsAvailable() local
1699 Type *VT = Root.getType(); maybeCreateShadowValue() local
1723 Type *VT = Op->getType(); maybeCreateShadowValue() local
1743 propagateFTStore(StoreInst & Store,Type * VT,Type * ExtendedVT,const ValueToShadowMap & Map) propagateFTStore() argument
1776 propagateNonFTStore(StoreInst & Store,Type * VT,const ValueToShadowMap & Map) propagateNonFTStore() argument
1891 Type *VT = StoredValue->getType(); propagateShadowValues() local
1922 Type *VT = RV->getType(); propagateShadowValues() local
1944 Type *VT = V->getType(); propagateShadowValues() local
[all...]
/llvm-project/libcxx/test/std/utilities/smartptr/unique.ptr/unique.ptr.class/unique.ptr.asgn/
H A Dmove.pass.cpp37 typedef typename std::conditional<IsArray, A[], A>::type VT; in test_basic() typedef
100 typedef typename std::conditional<IsArray, int[], int>::type VT; in test_sfinae() typedef
/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetTransformInfo.cpp14 EVT VT = TLI->getValueType(DL, DataType); in hasDivRemOp() local
/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp47 MVT VT = Node->getSimpleValueType(0); in INITIALIZE_PASS() local
209 MVT VT = Addr.getSimpleValueType(); SelectAddrConstant() local
275 EVT VT = N.getValueType(); selectShiftMask() local
302 MVT VT = N.getSimpleValueType(); selectSExti32() local
319 MVT VT = N.getSimpleValueType(); selectZExti32() local
[all...]
/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp167 EVT VT = N->getValueType(0); SelectExtractHigh() local
181 EVT VT = Op.getValueType(); SelectRoundingVLShr() local
725 EVT VT = N.getValueType(); SelectShiftedRegisterFromAnd() local
1466 EVT VT = N->getValueType(0); SelectTable() local
1488 EVT VT = LD->getMemoryVT(); tryIndexedLoad() local
1588 EVT VT = N->getValueType(0); SelectLoad() local
1617 EVT VT = N->getValueType(0); SelectPostLoad() local
1681 SelectOpcodeFromVT(EVT VT,ArrayRef<unsigned> Opcodes) SelectOpcodeFromVT() argument
1740 EVT VT = N->getValueType(0); SelectPExtPair() local
1754 EVT VT = N->getValueType(0); SelectWhilePair() local
1770 EVT VT = N->getValueType(0); SelectCVTIntrinsic() local
1791 EVT VT = N->getValueType(0); SelectDestructiveMultiIntrinsic() local
1827 EVT VT = N->getValueType(0); SelectPredicatedLoad() local
1862 EVT VT = N->getValueType(0); SelectContiguousMultiVectorLoad() local
1909 EVT VT = Node->getValueType(0); SelectMultiVectorLuti() local
1928 EVT VT = N->getValueType(0); SelectClamp() local
1997 EVT VT = N->getValueType(0); SelectMultiVectorMove() local
2033 EVT VT = N->getValueType(0); SelectMultiVectorMoveZ() local
2050 EVT VT = N->getValueType(0); SelectUnaryMultiIntrinsic() local
2078 EVT VT = N->getOperand(2)->getValueType(0); SelectStore() local
2140 EVT VT = N->getOperand(2)->getValueType(0); SelectPostStore() local
2168 EVT VT = V64Reg.getValueType(); operator ()() local
2184 EVT VT = V128Reg.getValueType(); NarrowVector() local
2196 EVT VT = N->getValueType(0); SelectLoadLane() local
2234 EVT VT = N->getValueType(0); SelectPostLoadLane() local
2288 EVT VT = N->getOperand(2)->getValueType(0); SelectStoreLane() local
2316 EVT VT = N->getOperand(2)->getValueType(0); SelectPostStoreLane() local
2354 EVT VT = N->getValueType(0); isBitfieldExtractOpFromAnd() local
2445 EVT VT = N->getValueType(0); isBitfieldExtractOpFromSExtInReg() local
2519 EVT VT = N->getValueType(0); isBitfieldExtractOpFromShr() local
2583 EVT VT = N->getValueType(0); tryBitfieldExtractOpFromSExt() local
2651 EVT VT = N->getValueType(0); tryBitfieldExtractOp() local
2678 isBitfieldDstMask(uint64_t DstMask,const APInt & BitsToBeInserted,unsigned NumberOfIgnoredHighBits,EVT VT) isBitfieldDstMask() argument
2915 EVT VT = Op.getValueType(); getLeftShift() local
2958 EVT VT = Op.getValueType(); isBitfieldPositioningOp() local
2992 EVT VT = Op.getValueType(); isBitfieldPositioningOpFromAnd() local
3114 EVT VT = Op.getValueType(); isBitfieldPositioningOpFromShl() local
3139 isShiftedMask(uint64_t Mask,EVT VT) isShiftedMask() argument
3151 EVT VT = N->getValueType(0); tryBitfieldInsertOpFromOrAndImm() local
3243 EVT VT = Dst.getValueType(); isWorthFoldingIntoOrrWithShift() local
3314 EVT VT = N->getValueType(0); tryOrrWithShift() local
3415 EVT VT = N->getValueType(0); tryBitfieldInsertOpFromOr() local
3485 EVT VT = OrOpd1Val.getValueType(); tryBitfieldInsertOpFromOr() local
3611 EVT VT = N->getValueType(0); tryBitfieldInsertInZeroOp() local
3637 EVT VT = N->getValueType(0); tryShiftAmountMod() local
4034 SelectSVEAddSubImm(SDValue N,MVT VT,SDValue & Imm,SDValue & Shift) SelectSVEAddSubImm() argument
4074 SelectSVEAddSubSSatImm(SDValue N,MVT VT,SDValue & Imm,SDValue & Shift,bool Negate) SelectSVEAddSubSSatImm() argument
4124 SelectSVECpyDupImm(SDValue N,MVT VT,SDValue & Imm,SDValue & Shift) SelectSVECpyDupImm() argument
4176 SelectSVEArithImm(SDValue N,MVT VT,SDValue & Imm) SelectSVEArithImm() argument
4204 SelectSVELogicalImm(SDValue N,MVT VT,SDValue & Imm,bool Invert) SelectSVELogicalImm() argument
4335 EVT VT = N->getValueType(0); trySelectCastFixedLengthToScalableVector() local
4364 EVT VT = N->getValueType(0); trySelectCastScalableToFixedLengthVector() local
4390 EVT VT = N->getValueType(0); trySelectXAR() local
4482 EVT VT = Node->getValueType(0); Select() local
7220 EVT VT = N.getValueType(); SelectAnyPredicate() local
[all...]
H A DAArch64ISelLowering.cpp171 static inline EVT getPackedSVEVectorVT(EVT VT) { in getPackedSVEVectorVT() argument
211 static inline EVT getPromotedVTForPredicate(EVT VT) { in getPromotedVTForPredicate() argument
233 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType() argument
452 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) AArch64TargetLowering() local
456 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) AArch64TargetLowering() local
631 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
683 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
1028 for (MVT VT : MVT::fp_valuetypes()) { AArch64TargetLowering() local
1035 for (MVT VT : MVT::integer_valuetypes()) AArch64TargetLowering() local
1317 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
1388 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
1543 for (MVT VT : MVT::scalable_vector_valuetypes()) { AArch64TargetLowering() local
1675 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
1680 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { AArch64TargetLowering() local
1817 addTypeForNEON(MVT VT) addTypeForNEON() argument
1967 addTypeForFixedLengthSVE(MVT VT) addTypeForFixedLengthSVE() argument
2109 addDRType(MVT VT) addDRType() argument
2115 addQRType(MVT VT) addQRType() argument
2223 EVT VT = Op.getValueType(); optimizeLogicalImm() local
2254 EVT VT = Op.getValueType(); targetShrinkDemandedConstant() local
2367 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); computeKnownBitsForTargetNode() local
2382 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); computeKnownBitsForTargetNode() local
2398 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); computeKnownBitsForTargetNode() local
2419 EVT VT = Op.getValueType(); ComputeNumSignBitsForTargetNode() local
2454 allowsMisalignedMemoryAccesses(EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMisalignedMemoryAccesses() argument
3412 EVT VT = LHS.getValueType(); emitStrictFPComparison() local
3432 EVT VT = LHS.getValueType(); emitComparison() local
3803 EVT VT = Op.getValueType(); getCmpOperandFoldingProfit() local
3815 EVT VT = RHS.getValueType(); getAArch64Cmp() local
4120 EVT VT = Value.getValueType(); valueToCarryFlag() local
4130 carryFlagToValue(SDValue Glue,EVT VT,SelectionDAG & DAG,bool Invert) carryFlagToValue() argument
4142 overflowFlagToValue(SDValue Glue,EVT VT,SelectionDAG & DAG) overflowFlagToValue() argument
4239 EVT VT = Op.getValueType(); LowerFP_EXTEND() local
4252 EVT VT = Op.getValueType(); LowerFP_ROUND() local
4340 EVT VT = Op.getValueType(); LowerVectorFP_TO_INT() local
4591 EVT VT = Op.getValueType(); LowerVectorXRINT() local
4615 EVT VT = Op.getValueType(); LowerVectorINT_TO_FP() local
4958 EVT VT = OpNode->getOperand(0).getValueType(); getConstantLaneNumOfExtractHalfOperand() local
4968 EVT VT = N.getValueType(); isExtendedBUILD_VECTOR() local
4993 EVT VT = N.getValueType(); skipExtensionForVectorMULL() local
5217 EVT VT = N0.getValueType(); selectUmullSmull() local
5246 EVT VT = Op.getValueType(); LowerMUL() local
5324 getPTrue(SelectionDAG & DAG,SDLoc DL,EVT VT,int Pattern) getPTrue() argument
5370 getSVEPredicateBitCast(EVT VT,SDValue Op,SelectionDAG & DAG) getSVEPredicateBitCast() argument
5999 EVT VT = Op.getValueType(); LowerINTRINSIC_WO_CHAIN() local
6034 EVT VT = CttzOp.getValueType(); LowerINTRINSIC_WO_CHAIN() local
6052 shouldExtendGSIndex(EVT VT,EVT & EltTy) const shouldExtendGSIndex() argument
6163 EVT VT = Op.getValueType(); LowerMGATHER() local
6262 EVT VT = StoreVal.getValueType(); LowerMSCATTER() local
6336 EVT VT = Op->getValueType(0); LowerMLOAD() local
6360 LowerTruncateVectorStore(SDLoc DL,StoreSDNode * ST,EVT VT,EVT MemVT,SelectionDAG & DAG) LowerTruncateVectorStore() argument
6401 EVT VT = Value.getValueType(); LowerSTORE() local
6527 EVT VT = Op->getValueType(0); LowerLOAD() local
6561 MVT VT = Op.getSimpleValueType(); LowerABS() local
6602 MVT VT = Op.getSimpleValueType(); LowerFunnelShift() local
7007 useSVEForFixedLengthVectorVT(EVT VT,bool OverrideNEON) const useSVEForFixedLengthVectorVT() argument
7156 isPassedInFPR(EVT VT) isPassedInFPR() argument
9560 LowerPtrAuthGlobalAddressStatically(SDValue TGA,SDLoc DL,EVT VT,AArch64PACKey::ID KeyC,SDValue Discriminator,SDValue AddrDiscriminator,SelectionDAG & DAG) const LowerPtrAuthGlobalAddressStatically() argument
9589 EVT VT = Op.getValueType(); LowerPtrAuthGlobalAddress() local
9815 EVT VT = Op.getValueType(); LowerFCOPYSIGN() local
9841 __anonb71a9e6e0e02(EVT VT, SDValue Op, SelectionDAG &DAG) LowerFCOPYSIGN() argument
9908 EVT VT = Op.getValueType(); LowerCTPOP_PARITY() local
10009 EVT VT = Op.getValueType(); LowerCTTZ() local
10022 EVT VT = Op.getValueType(); LowerMinMax() local
10068 EVT VT = Op.getValueType(); LowerBitreverse() local
10149 EVT VT = N->getValueType(0); performOrXorChainCombine() local
10197 EVT VT = Op.getValueType(); LowerSETCC() local
10273 EVT VT = LHS.getValueType(); LowerSETCCCARRY() local
10336 EVT VT = LHS.getValueType(); LowerSELECT_CC() local
10350 EVT VT = LHS.getValueType(); LowerSELECT_CC() local
10475 EVT VT = TVal.getValueType(); LowerSELECT_CC() local
10483 EVT VT = TVal.getValueType(); LowerSELECT_CC() local
10878 EVT VT = Op.getValueType(); LowerVAARG() local
10948 EVT VT = Op.getValueType(); LowerFRAMEADDR() local
10968 EVT VT = getPointerTy(DAG.getDataLayout()); LowerSPONENTRY() local
10980 getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const getRegisterByName() argument
10999 EVT VT = Op.getValueType(); LowerADDROFRETURNADDR() local
11015 EVT VT = Op.getValueType(); LowerRETURNADDR() local
11064 isFPImmLegal(const APFloat & Imm,EVT VT,bool OptForSize) const isFPImmLegal() argument
11114 EVT VT = Operand.getValueType(); getEstimate() local
11145 EVT VT = Op.getValueType(); getSqrtInputTest() local
11167 EVT VT = Operand.getValueType(); getSqrtEstimate() local
11197 EVT VT = Operand.getValueType(); getRecipEstimate() local
11278 getPredicateRegisterClass(PredicateConstraint Constraint,EVT VT) getPredicateRegisterClass() argument
11309 getReducedGprRegisterClass(ReducedGprConstraint Constraint,EVT VT) getReducedGprRegisterClass() argument
11729 EVT VT = V64Reg.getValueType(); WidenVector() local
11752 EVT VT = Op.getValueType(); ReconstructShuffleWithRuntimeMask() local
11845 EVT VT = Op.getValueType(); ReconstructShuffle() local
12139 isSingletonEXTMask(ArrayRef<int> M,EVT VT,unsigned & Imm) isSingletonEXTMask() argument
12222 isWideDUPMask(ArrayRef<int> M,EVT VT,unsigned BlockSize,unsigned & DupLaneOp) isWideDUPMask() argument
12295 isEXTMask(ArrayRef<int> M,EVT VT,bool & ReverseEXT,unsigned & Imm) isEXTMask() argument
12337 isZIP_v_undef_Mask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isZIP_v_undef_Mask() argument
12356 isUZP_v_undef_Mask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isUZP_v_undef_Mask() argument
12375 isTRN_v_undef_Mask(ArrayRef<int> M,EVT VT,unsigned & WhichResult) isTRN_v_undef_Mask() argument
12427 isConcatMask(ArrayRef<int> Mask,EVT VT,bool SplitLHS) isConcatMask() argument
12449 EVT VT = Op.getValueType(); tryFormConcatFromShuffle() local
12531 EVT VT = OpLHS.getValueType(); GeneratePerfectShuffle() local
12579 EVT VT = OpLHS.getValueType(); GeneratePerfectShuffle() local
12728 constructDup(SDValue V,int Lane,SDLoc dl,EVT VT,unsigned Opcode,SelectionDAG & DAG) constructDup() argument
12790 isWideTypeMask(ArrayRef<int> M,EVT VT,SmallVectorImpl<int> & NewMask) isWideTypeMask() argument
12837 EVT VT = Op.getValueType(); tryWidenMaskForShuffle() local
12877 EVT VT = Op.getValueType(); tryToConvertShuffleOfTbl2ToTbl4() local
12919 EVT VT = Op.getValueType(); LowerZERO_EXTEND_VECTOR_INREG() local
12936 EVT VT = Op.getValueType(); LowerVECTOR_SHUFFLE() local
13111 EVT VT = Op.getValueType(); LowerSPLAT_VECTOR() local
13144 EVT VT = Op.getValueType(); LowerDUPQLane() local
13188 EVT VT = BVN->getValueType(0); resolveBuildVector() local
13213 EVT VT = Op.getValueType(); tryAdvSIMDModImm64() local
13233 EVT VT = Op.getValueType(); tryAdvSIMDModImm32() local
13286 EVT VT = Op.getValueType(); tryAdvSIMDModImm16() local
13332 EVT VT = Op.getValueType(); tryAdvSIMDModImm321s() local
13363 EVT VT = Op.getValueType(); tryAdvSIMDModImm8() local
13384 EVT VT = Op.getValueType(); tryAdvSIMDModImmFP() local
13421 EVT VT = Bvec->getValueType(0); isAllConstantBuildVector() local
13484 EVT VT = N->getValueType(0); tryLowerToSLI() local
13594 EVT VT = Op.getValueType(); LowerVectorOR() local
13637 EVT VT = Op.getValueType(); NormalizeBuildVector() local
13666 EVT VT = Op.getValueType(); ConstantBuildVector() local
13739 EVT VT = Op.getValueType(); LowerBUILD_VECTOR() local
14227 EVT VT = Op.getOperand(0).getValueType(); LowerINSERT_VECTOR_ELT() local
14257 EVT VT = Op.getOperand(0).getValueType(); LowerEXTRACT_VECTOR_ELT() local
14308 EVT VT = Op.getValueType(); LowerEXTRACT_SUBVECTOR() local
14370 EVT VT = Op.getValueType(); LowerINSERT_SUBVECTOR() local
14480 EVT VT = Op.getValueType(); LowerDIV() local
14529 shouldExpandBuildVectorWithShuffles(EVT VT,unsigned DefinedValues) const shouldExpandBuildVectorWithShuffles() argument
14597 isVShiftLImm(SDValue Op,EVT VT,bool isLong,int64_t & Cnt) isVShiftLImm() argument
14608 isVShiftRImm(SDValue Op,EVT VT,bool isNarrow,int64_t & Cnt) isVShiftRImm() argument
14618 EVT VT = Op.getValueType(); LowerTRUNCATE() local
14650 EVT VT = Shift.getValueType(); canLowerSRLToRoundingShiftForVT() local
14687 EVT VT = Op.getValueType(); LowerVectorSRA_SRL_SHL() local
14755 EmitVectorComparison(SDValue LHS,SDValue RHS,AArch64CC::CondCode CC,bool NoNans,EVT VT,const SDLoc & dl,SelectionDAG & DAG) EmitVectorComparison() argument
14964 getVectorBitwiseReduce(unsigned Opcode,SDValue Vec,EVT VT,SDLoc DL,SelectionDAG & DAG) getVectorBitwiseReduce() argument
15148 MVT VT = Op.getSimpleValueType(); LowerATOMIC_LOAD_AND() local
15169 EVT VT = Node->getValueType(0); LowerWindowsDYNAMIC_STACKALLOC() local
15235 EVT VT = Node->getValueType(0); LowerInlineDYNAMIC_STACKALLOC() local
15275 EVT VT = Op.getValueType(); LowerVSCALE() local
15291 const EVT VT = TLI.getMemValueType(DL, CI.getArgOperand(0)->getType()); setInfoSVEStN() local
15524 EVT VT = Extend.getValueType(); shouldRemoveRedundantExtend() local
17000 __anonb71a9e6e1d02(EVT VT, Align AlignCheck) getOptimalMemOpType() argument
17030 __anonb71a9e6e1e02(EVT VT, Align AlignCheck) getOptimalMemOpLLT() argument
17105 const EVT VT = AddNode.getValueType(); isMulAddWithConstProfitable() local
17263 generateFMAsInMachineCombiner(EVT VT,CodeGenOptLevel OptLevel) const generateFMAsInMachineCombiner() argument
17292 EVT VT = N->getValueType(0); isDesirableToCommuteWithShift() local
17351 EVT VT = N->getValueType(0); shouldFoldConstantShiftPairToMask() local
17402 EVT VT = N->getValueType(0); foldVectorXorShiftIntoCmp() local
17627 EVT VT = A.getValueType(); performUADDVAddCombine() local
17675 EVT VT = A.getValueType(); performUADDVZextCombine() local
17737 EVT VT = N->getValueType(0); BuildSDIVPow2() local
17760 EVT VT = N->getValueType(0); BuildSREMPow2() local
17872 EVT VT = BV.getValueType(); performBuildShuffleExtendCombine() local
17937 EVT VT = Mul->getValueType(0); performMulVectorExtendCombine() local
17956 EVT VT = N->getValueType(0); performMulVectorCmpZeroCombine() local
17993 EVT VT = N->getValueType(0); performVectorExtCombine() local
18047 EVT VT = N->getValueType(0); performMulCombine() local
18292 EVT VT = N->getValueType(0); performVectorCompareAndMaskUnaryOpCombine() local
18332 EVT VT = N->getValueType(0); performIntToFpCombine() local
18438 EVT VT = N->getValueType(0); tryCombineToBSL() local
18547 EVT VT = N->getValueType(0); performANDORCSELCombine() local
18618 EVT VT = N->getValueType(0); performORCombine() local
18691 __anonb71a9e6e2802(EVT VT) performSVEAndCombine() argument
18790 EVT VT = N->getValueType(0); performANDSETCCCombine() local
18827 EVT VT = N->getValueType(0); performANDCombine() local
18890 EVT VT = N->getValueType(0); performFADDCombine() local
18921 hasPairwiseAdd(unsigned Opcode,EVT VT,bool FullFP16) hasPairwiseAdd() argument
18966 EVT VT = N0.getValueType(); performFirstTrueTestVectorCombine() local
19032 EVT VT = N->getValueType(0); performExtractVectorEltCombine() local
19094 EVT VT = N->getValueType(0); performConcatVectorsCombine() local
19228 EVT VT = Op.getValueType(); performConcatVectorsCombine() local
19323 EVT VT = N->getValueType(0); performExtractSubvectorCombine() local
19446 MVT VT = N.getSimpleValueType(); tryExtendDUPToExtractHigh() local
19627 EVT VT = Op->getValueType(0); performSetccAddFolding() local
19634 EVT VT = N->getValueType(0); performAddUADDVCombine() local
19673 EVT VT = N->getValueType(0); performAddCSelIntoCSinc() local
19746 EVT VT = N->getValueType(0); performAddDotCombine() local
19773 EVT VT = Op.getValueType(); getNegatedInteger() local
19805 EVT VT = CSel.getValueType(); performNegCSelCombine() local
19827 MVT VT = N->getSimpleValueType(0); performAddSubLongCombine() local
19920 EVT VT = N->getValueType(0); foldADCToCINC() local
19932 EVT VT = N->getValueType(0); performBuildVectorCombine() local
20066 EVT VT = N->getValueType(0); performTruncateCombine() local
20127 EVT VT = N->getValueType(0); performAddCombineSubShift() local
20143 EVT VT = N->getValueType(0); performAddCombineForShiftedOperands() local
20198 EVT VT = N->getValueType(0); performSubAddMULCombine() local
20261 EVT VT = N->getValueType(0); performAddSubIntoVectorOp() local
20421 EVT VT = N->getValueType(0); performExtBinopLoadFold() local
20670 EVT VT = N->getValueType(0); tryCombineShiftImm() local
20756 EVT VT = N->getValueType(0); LowerSVEIntrinsicEXT() local
20789 EVT VT = N->getValueType(0); tryConvertSVEWideCompare() local
20843 getPTest(SelectionDAG & DAG,EVT VT,SDValue Pg,SDValue Op,AArch64CC::CondCode Cond) getPTest() argument
21472 EVT VT = N->getValueType(0); performLD1Combine() local
21498 EVT VT = N->getValueType(0); performLDNT1Combine() local
21527 EVT VT = N->getValueType(0); performLD1ReplicateCombine() local
21603 EVT VT = StVal.getValueType(); replaceZeroVectorStore() local
21670 EVT VT = StVal.getValueType(); replaceSplatVectorStore() local
21730 EVT VT = StVal.getValueType(); splitStores() local
21827 EVT VT = N->getValueType(0); performUnpackCombine() local
21907 EVT VT = Srl->getValueType(0); trySimplifySrlAddToRshrnb() local
22201 auto VT = CC->getValueType(0).getHalfNumVectorElementsVT(*DAG.getContext()); performSunpkloCombine() local
22219 EVT VT = N->getValueType(0); performPostLD1Combine() local
22620 EVT VT = VecOp.getValueType(); combineBoolVectorAndTruncateStore() local
22707 __anonb71a9e6e3202(EVT VT) performSTORECombine() argument
23573 EVT VT = Op->getValueType(0); foldCSELOfCSEL() local
23670 EVT VT = N->getValueType(0); performSETCCCombine() local
23744 EVT VT = N->getValueType(0); performFlagSettingCombine() local
24008 EVT VT = CmpLHS.getValueType(); performVSelectCombine() local
24126 EVT VT = N->getValueType(0); performDUPCombine() local
24529 auto VT = cast<VTSDNode>(N->getOperand(1))->getVT(); performSignExtendInRegCombine() local
24755 EVT VT = N->getValueType(0); performFPExtendCombine() local
24761 __anonb71a9e6e3402(EVT VT) performFPExtendCombine() argument
24791 EVT VT = N->getValueType(0); performBSPExpandForSVE() local
24810 EVT VT = N->getValueType(0); performDupLane128Combine() local
25008 EVT VT = N->getValueType(0); performScalarToVectorCombine() local
25501 EVT VT; getPreIndexedAddressParts() local
25521 EVT VT; getPostIndexedAddressParts() local
25547 EVT VT = N->getValueType(0); replaceBoolVectorBitcast() local
25575 EVT VT = N->getValueType(0); CustomNonLegalBITCASTResults() local
25589 EVT VT = N->getValueType(0); ReplaceBITCASTResults() local
25640 EVT VT = N->getValueType(0); ReplaceAddWithADDP() local
25709 EVT VT = N->getValueType(0); ReplaceExtractSubVectorResults() local
26111 EVT VT = N->getValueType(0); ReplaceNodeResults() local
26694 isIntDivCheap(EVT VT,AttributeList Attr) const isIntDivCheap() argument
26902 getContainerForFixedLengthVector(SelectionDAG & DAG,EVT VT) getContainerForFixedLengthVector() argument
26930 getPredicateForFixedLengthVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForFixedLengthVector() argument
26975 getPredicateForScalableVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForScalableVector() argument
26982 getPredicateForVector(SelectionDAG & DAG,SDLoc & DL,EVT VT) getPredicateForVector() argument
26990 convertToScalableVector(SelectionDAG & DAG,EVT VT,SDValue V) convertToScalableVector() argument
27001 convertFromScalableVector(SelectionDAG & DAG,EVT VT,SDValue V) convertFromScalableVector() argument
27017 EVT VT = Op.getValueType(); LowerFixedLengthVectorLoadToSVE() local
27075 EVT VT = Op.getValueType(); LowerFixedLengthVectorMLoadToSVE() local
27126 EVT VT = Store->getValue().getValueType(); LowerFixedLengthVectorStoreToSVE() local
27159 EVT VT = Store->getValue().getValueType(); LowerFixedLengthVectorMStoreToSVE() local
27174 EVT VT = Op.getValueType(); LowerFixedLengthVectorIntDivideToSVE() local
27239 EVT VT = Op.getValueType(); LowerFixedLengthVectorIntExtendToSVE() local
27275 EVT VT = Op.getValueType(); LowerFixedLengthVectorTruncateToSVE() local
27311 EVT VT = Op.getValueType(); LowerFixedLengthExtractVectorElt() local
27324 EVT VT = Op.getValueType(); LowerFixedLengthInsertVectorElt() local
27344 EVT VT = Op.getValueType(); LowerToPredicatedOp() local
27400 EVT VT = Op.getValueType(); LowerToScalableOp() local
27460 EVT VT = ReduceOp.getValueType(); LowerPredReductionToSVE() local
27534 EVT VT = Op.getValueType(); LowerFixedLengthVectorSelectToSVE() local
27585 EVT VT = Op.getValueType(); LowerFixedLengthBitcastToSVE() local
27605 EVT VT = Op.getValueType(); LowerFixedLengthConcatVectorsToSVE() local
27632 EVT VT = Op.getValueType(); LowerFixedLengthFPExtendToSVE() local
27657 EVT VT = Op.getValueType(); LowerFixedLengthFPRoundToSVE() local
27681 EVT VT = Op.getValueType(); LowerFixedLengthIntToFPToSVE() local
27811 EVT VT = Op.getValueType(); LowerFixedLengthFPToIntToSVE() local
27852 GenerateFixedLengthSVETBL(SDValue Op,SDValue Op1,SDValue Op2,ArrayRef<int> ShuffleMask,EVT VT,EVT ContainerVT,SelectionDAG & DAG) GenerateFixedLengthSVETBL() argument
27965 EVT VT = Op.getValueType(); LowerFixedLengthVECTOR_SHUFFLEToSVE() local
28121 getSVESafeBitCast(EVT VT,SDValue Op,SelectionDAG & DAG) const getSVESafeBitCast() argument
28440 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const getVectorTypeBreakdownForCallingConv() argument
28522 EVT VT = N->getValueType(0); verifyTargetSDNode() local
28541 EVT VT = N->getValueType(0); verifyTargetSDNode() local
[all...]
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp198 for (MVT VT : IntVecVTs) { in RISCVTargetLowering() local
202 addRegClassForRVV(VT); in RISCVTargetLowering() local
206 for (MVT VT in RISCVTargetLowering() local
165 __anon17a3f42a0102(MVT VT) RISCVTargetLowering() argument
188 for (MVT VT : BoolVecVTs) RISCVTargetLowering() local
190 for (MVT VT : IntVecVTs) { RISCVTargetLowering() local
210 for (MVT VT : F64VecVTs) RISCVTargetLowering() local
214 __anon17a3f42a0202(MVT VT) RISCVTargetLowering() argument
220 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) RISCVTargetLowering() local
224 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) RISCVTargetLowering() local
750 for (MVT VT : BoolVecVTs) { RISCVTargetLowering() local
820 for (MVT VT : IntVecVTs) { RISCVTargetLowering() local
973 __anon17a3f42a0302(MVT VT) RISCVTargetLowering() argument
1051 __anon17a3f42a0402(MVT VT, ArrayRef<MVT::SimpleValueType> SmallerVTs) RISCVTargetLowering() argument
1059 for (MVT VT : F16VecVTs) { RISCVTargetLowering() local
1065 for (MVT VT : F16VecVTs) { RISCVTargetLowering() local
1101 for (MVT VT : BF16VecVTs) { RISCVTargetLowering() local
1122 for (MVT VT : F32VecVTs) { RISCVTargetLowering() local
1131 for (MVT VT : F64VecVTs) { RISCVTargetLowering() local
1141 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { RISCVTargetLowering() local
1290 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { RISCVTargetLowering() local
1950 EVT VT = Y.getValueType(); hasAndNotCompare() local
2241 isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const isFPImmLegal() argument
2356 getVectorTypeBreakdownForCallingConv(LLVMContext & Context,CallingConv::ID CC,EVT VT,EVT & IntermediateVT,unsigned & NumIntermediates,MVT & RegisterVT) const getVectorTypeBreakdownForCallingConv() argument
2436 getLMUL(MVT VT) getLMUL() argument
2480 getSubregIndexByMVT(MVT VT,unsigned Index) getSubregIndexByMVT() argument
2503 getRegClassIDForVecVT(MVT VT) getRegClassIDForVecVT() argument
2593 useRVVForFixedLengthVectorVT(MVT VT,const RISCVSubtarget & Subtarget) useRVVForFixedLengthVectorVT() argument
2669 getContainerForFixedLengthVector(const TargetLowering & TLI,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2704 getContainerForFixedLengthVector(SelectionDAG & DAG,MVT VT,const RISCVSubtarget & Subtarget) getContainerForFixedLengthVector() argument
2715 convertToScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertToScalableVector() argument
2727 convertFromScalableVector(EVT VT,SDValue V,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) convertFromScalableVector() argument
2835 shouldExpandBuildVectorWithShuffles(EVT VT,unsigned DefinedValues) const shouldExpandBuildVectorWithShuffles() argument
3029 MVT VT = Op.getSimpleValueType(); lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local
3139 MVT VT = Op.getSimpleValueType(); lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local
3239 MVT VT = Op.getSimpleValueType(); lowerFTRUNC_FCEIL_FFLOOR_FROUND() local
3267 MVT VT = Op.getSimpleValueType(); lowerVectorXRINT() local
3291 getVSlidedown(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlidedown() argument
3303 getVSlideup(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlideup() argument
3313 getLMUL1VT(MVT VT) getLMUL1VT() argument
3458 matchSplatAsGather(SDValue SplatVal,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) matchSplatAsGather() argument
3502 MVT VT = Op.getSimpleValueType(); lowerBuildVectorViaDominantValues() local
3609 MVT VT = Op.getSimpleValueType(); lowerBuildVectorOfConstants() local
3916 MVT VT = Op.getSimpleValueType(); lowerBuildVectorViaPacking() local
3969 MVT VT = Op.getSimpleValueType(); lowerBUILD_VECTORvXf16() local
3980 MVT VT = Op.getSimpleValueType(); lowerBUILD_VECTOR() local
4206 splatPartsI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Lo,SDValue Hi,SDValue VL,SelectionDAG & DAG) splatPartsI64WithVL() argument
4262 splatSplitI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Scalar,SDValue VL,SelectionDAG & DAG) splatSplitI64WithVL() argument
4275 lowerScalarSplat(SDValue Passthru,SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarSplat() argument
4312 lowerScalarInsert(SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarInsert() argument
4372 isDeinterleaveShuffle(MVT VT,MVT ContainerVT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget) isDeinterleaveShuffle() argument
4417 isInterleaveShuffle(ArrayRef<int> Mask,MVT VT,int & EvenSrc,int & OddSrc,const RISCVSubtarget & Subtarget) isInterleaveShuffle() argument
4527 getDeinterleaveViaVNSRL(const SDLoc & DL,MVT VT,SDValue Src,bool EvenElts,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) getDeinterleaveViaVNSRL() argument
4586 lowerVECTOR_SHUFFLEAsVSlidedown(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlidedown() argument
4663 lowerVECTOR_SHUFFLEAsVSlideup(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlideup() argument
4707 lowerVECTOR_SHUFFLEAsVSlide1(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlide1() argument
4865 MVT VT = SVN->getSimpleValueType(0); lowerBitreverseShuffle() local
4919 EVT VT = SVN->getValueType(0); isLegalBitRotate() local
4941 EVT VT = SVN->getValueType(0); lowerVECTOR_SHUFFLEAsRotate() local
4968 MVT VT = SVN->getSimpleValueType(0); lowerShuffleViaVRegSplitting() local
5052 MVT VT = Op.getSimpleValueType(); lowerVECTOR_SHUFFLE() local
5398 MVT VT = Op.getSimpleValueType(); lowerCTLZ_CTTZ_ZERO_UNDEF() local
5565 MVT VT = Op.getSimpleValueType(); expandUnalignedRVVLoad() local
5596 MVT VT = StoredVal.getSimpleValueType(); expandUnalignedRVVStore() local
5754 MVT VT = Op.getSimpleValueType(); LowerIS_FPCLASS() local
5856 MVT VT = Op.getSimpleValueType(); lowerFMAXIMUM_FMINIMUM() local
6291 EVT VT = Op.getValueType(); LowerOperation() local
6373 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6408 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6429 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6485 EVT VT = Op.getValueType(); LowerOperation() local
6502 EVT VT = Op.getValueType(); LowerOperation() local
6565 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6714 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6861 MVT VT = Op.getSimpleValueType(); LowerOperation() local
6926 EVT VT = Op.getValueType(); LowerOperation() local
6939 MVT VT = Op.getSimpleValueType(); LowerOperation() local
7041 EVT VT = Op->getValueType(0); LowerOperation() local
7554 MVT VT = N->getSimpleValueType(0); combineSelectToBinOp() local
7657 EVT VT = BO->getValueType(0); foldBinOpIntoSelectIfProfitable() local
7688 MVT VT = Op.getSimpleValueType(); lowerSELECT() local
7908 EVT VT = Op.getValueType(); lowerFRAMEADDR() local
7934 EVT VT = Op.getValueType(); lowerRETURNADDR() local
7958 EVT VT = Lo.getValueType(); lowerShiftLeftParts() local
7997 EVT VT = Lo.getValueType(); lowerShiftRightParts() local
8048 MVT VT = Op.getSimpleValueType(); lowerVectorMaskSplat() local
8145 MVT VT = Op.getOperand(0).getSimpleValueType(); lowerFixedLengthVectorExtendToRVV() local
8226 MVT VT = Op.getSimpleValueType(); lowerVectorTruncLike() local
8289 MVT VT = Op.getSimpleValueType(); lowerStrictFPExtendOrRoundLike() local
8343 MVT VT = Op.getSimpleValueType(); lowerVectorFPExtendOrRoundLike() local
8807 MVT VT = Op.getOperand(SplatOp - 1).getSimpleValueType(); lowerVectorIntrinsicScalars() local
9062 isValidEGW(int EGS,EVT VT,const RISCVSubtarget & Subtarget) isValidEGW() argument
9238 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
9318 MVT VT = Op.getSimpleValueType(); LowerINTRINSIC_WO_CHAIN() local
9355 MVT VT = Op.getSimpleValueType(); getVCIXISDNodeWCHAIN() local
9408 MVT VT = Op->getSimpleValueType(0); LowerINTRINSIC_W_CHAIN() local
9490 MVT VT = Op->getSimpleValueType(0); LowerINTRINSIC_W_CHAIN() local
9563 MVT VT = Val.getSimpleValueType(); LowerINTRINSIC_VOID() local
9611 MVT VT = Op->getOperand(2).getSimpleValueType(); LowerINTRINSIC_VOID() local
10414 MVT VT = N.getSimpleValueType(); widenVectorOpsToi8() local
10610 MVT VT = Op.getSimpleValueType(); lowerSTEP_VECTOR() local
10756 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorLoadToRVV() local
10806 MVT VT = StoreVal.getSimpleValueType(); lowerFixedLengthVectorStoreToRVV() local
10850 MVT VT = Op.getSimpleValueType(); lowerMaskedLoad() local
10938 MVT VT = Val.getSimpleValueType(); lowerMaskedStore() local
10983 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorSetccToRVV() local
11011 MVT VT = Op.getSimpleValueType(); lowerVectorStrictFSetcc() local
11093 MVT VT = Op.getSimpleValueType(); lowerABS() local
11131 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorFCOPYSIGNToRVV() local
11151 MVT VT = Op.getSimpleValueType(); lowerFixedLengthVectorSelectToRVV() local
11179 MVT VT = Op.getSimpleValueType(); lowerToScalableOp() local
11232 MVT VT = Op.getSimpleValueType(); lowerVPOp() local
11285 MVT VT = Op.getSimpleValueType(); lowerVPExtMaskOp() local
11318 MVT VT = Op.getSimpleValueType(); lowerVPSetCCMaskOp() local
11522 MVT VT = Op.getSimpleValueType(); lowerVPFPIntConvOp() local
11541 MVT VT = Op.getSimpleValueType(); lowerVPSpliceExperimental() local
11616 MVT VT = Op.getSimpleValueType(); lowerVPReverseExperimental() local
11735 MVT VT = Op.getSimpleValueType(); lowerLogicVPOp() local
11763 MVT VT = Op.getSimpleValueType(); lowerVPStridedLoad() local
11812 MVT VT = StoreVal.getSimpleValueType(); lowerVPStridedStore() local
11851 MVT VT = Op.getSimpleValueType(); lowerMaskedGather() local
11975 MVT VT = Val.getSimpleValueType(); lowerMaskedScatter() local
12409 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
12570 EVT VT = N->getValueType(0); ReplaceNodeResults() local
12611 MVT VT = N->getSimpleValueType(0); ReplaceNodeResults() local
12808 EVT VT = N->getValueType(0); ReplaceNodeResults() local
12928 const EVT VT = N->getValueType(0); combineBinOpOfExtractToReduceTree() local
13122 EVT VT = N->getValueType(0); transformAddShlImm() local
13173 EVT VT = N->getValueType(0); combineSelectAndUse() local
13268 EVT VT = N->getValueType(0); transformAddImmMulImm() local
13327 EVT VT = N->getValueType(0); combineBinOpOfZExt() local
13370 EVT VT = N->getValueType(0); combineAddOfBooleanXor() local
13418 EVT VT = N->getValueType(0); combineSubOfBoolean() local
13462 EVT VT = N->getValueType(0); combineSubShiftToOrcB() local
13489 EVT VT = N->getValueType(0); performSUBCombine() local
13544 EVT VT = N->getValueType(0); combineDeMorganOfBoolean() local
13568 EVT VT = N->getValueType(0); combineTruncSelectToSMaxUSat() local
13634 EVT VT = N->getValueType(0); performTRUNCATECombine() local
13720 EVT VT = N->getValueType(0); combineOrOfCZERO() local
13794 EVT VT = N0.getValueType(); performXORCombine() local
13835 EVT VT = N->getValueType(0); expandMul() local
13985 EVT VT = N->getValueType(0); combineVectorMulToSraBitcast() local
14023 EVT VT = N->getValueType(0); performMULCombine() local
14078 EVT VT = N.getValueType(); narrowIndex() local
14144 EVT VT = N->getValueType(0); performSETCCCombine() local
14190 EVT VT = N->getValueType(0); performSIGN_EXTEND_INREGCombine() local
14329 MVT VT = Root->getSimpleValueType(0); getNarrowType() local
14451 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupportForSplat() local
14504 MVT VT = OrigOperand.getSimpleValueType(); fillUpExtensionSupport() local
14627 MVT VT = Root->getSimpleValueType(0); getMaskAndVL() local
15242 EVT VT = N->getValueType(0); performFP_TO_INTCombine() local
15388 EVT VT = N->getValueType(0); performBITREVERSECombine() local
15673 EVT VT = Cond.getValueType(); tryDemorganOfBooleanCondition() local
15832 EVT VT = N->getValueType(0); tryFoldSelectIntoOp() local
15916 EVT VT = N->getValueType(0); useInversedSetcc() local
15968 EVT VT = N->getValueType(0); performBUILD_VECTORCombine() local
16030 EVT VT = InVec.getValueType(); performINSERT_VECTOR_ELTCombine() local
16098 EVT VT = N->getValueType(0); performCONCAT_VECTORSCombine() local
16290 EVT VT = N->getValueType(0); combineToVWMACC() local
16329 matchIndexAsShuffle(EVT VT,SDValue Index,SDValue Mask,SmallVector<int> & ShuffleMask) matchIndexAsShuffle() argument
16364 matchIndexAsWiderOp(EVT VT,SDValue Index,SDValue Mask,Align BaseAlign,const RISCVSubtarget & ST) matchIndexAsWiderOp() argument
16469 MVT VT = N->getSimpleValueType(0); combineTruncToVnclip() local
16696 MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
16728 EVT VT = N->getValueType(0); PerformDAGCombine() local
16862 EVT VT = N->getValueType(0); PerformDAGCombine() local
16977 EVT VT = N->getValueType(0); PerformDAGCombine() local
17002 const EVT VT = N->getValueType(0); PerformDAGCombine() local
17123 EVT VT = MSN->getValue()->getValueType(0); PerformDAGCombine() local
17196 EVT VT = N->getValueType(0); PerformDAGCombine() local
17218 EVT VT = N->getValueType(0); PerformDAGCombine() local
17363 EVT VT = N->getValueType(0); PerformDAGCombine() local
17385 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17396 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17428 EVT VT = N->getValueType(0); PerformDAGCombine() local
17439 const MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17492 MVT VT = N->getSimpleValueType(0); PerformDAGCombine() local
17540 EVT VT = N->getValueType(0); PerformDAGCombine() local
17551 EVT VT = N->getValueType(0); PerformDAGCombine() local
17651 EVT VT = Op.getValueType(); targetShrinkDemandedConstant() local
19821 getPrefTypeAlign(EVT VT,SelectionDAG & DAG) getPrefTypeAlign() argument
20138 MVT VT = Outs[i].VT; CanLowerReturn() local
21163 EVT VT; getPreIndexedAddressParts() local
21206 EVT VT; getPostIndexedAddressParts() local
21282 decomposeMulByConstant(LLVMContext & Context,EVT VT,SDValue C) const decomposeMulByConstant() argument
21324 EVT VT = AddNode.getValueType(); isMulAddWithConstProfitable() local
21345 allowsMisalignedMemoryAccesses(EVT VT,unsigned AddrSpace,Align Alignment,MachineMemOperand::Flags Flags,unsigned * Fast) const allowsMisalignedMemoryAccesses() argument
21514 isIntDivCheap(EVT VT,AttributeList Attr) const isIntDivCheap() argument
21557 EVT VT = getValueType(DL, VTy); isLegalInterleavedAccessType() local
21839 getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const getRegisterByName() argument
21913 getCustomCtpopCost(EVT VT,ISD::CondCode Cond) const getCustomCtpopCost() argument
21956 EVT VT = N->getValueType(0); BuildSDIVPow2() local
21967 shouldFoldSelectWithSingleBitTest(EVT VT,const APInt & AndMask) const shouldFoldSelectWithSingleBitTest() argument
22046 EVT VT = TLI->getValueType(DL, ElemTy); constructArgInfos() local
22060 EVT VT = ValueVTs[Value]; constructArgInfos() local
[all...]
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp40 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
183 for (MVT VT : MVT::integer_valuetypes()) in AMDGPUTargetLowering() local
187 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
199 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) AMDGPUTargetLowering() local
461 for (MVT VT : ScalarIntVTs) { AMDGPUTargetLowering() local
507 for (MVT VT : VectorIntTypes) { AMDGPUTargetLowering() local
528 for (MVT VT : FloatVectorTypes) { AMDGPUTargetLowering() local
709 opMustUseVOP3Encoding(const SDNode * N,MVT VT) opMustUseVOP3Encoding() argument
770 MVT VT = N->getValueType(0).getScalarType().getSimpleVT(); allUsesHaveSourceMods() local
788 getTypeForExtReturn(LLVMContext & Context,EVT VT,ISD::NodeType ExtendKind) const getTypeForExtReturn() argument
809 isFPImmLegal(const APFloat & Imm,EVT VT,bool ForCodeSize) const isFPImmLegal() argument
928 EVT VT = Op.getValueType(); getNegatedExpression() local
1518 EVT VT = Op.getValueType(); LowerCONCAT_VECTORS() local
1553 EVT VT = Op.getValueType(); LowerEXTRACT_SUBVECTOR() local
1602 combineFMinMaxLegacyImpl(const SDLoc & DL,EVT VT,SDValue LHS,SDValue RHS,SDValue True,SDValue False,SDValue CC,DAGCombinerInfo & DCI) const combineFMinMaxLegacyImpl() argument
1670 combineFMinMaxLegacy(const SDLoc & DL,EVT VT,SDValue LHS,SDValue RHS,SDValue True,SDValue False,SDValue CC,DAGCombinerInfo & DCI) const combineFMinMaxLegacy() argument
1743 getSplitDestVTs(const EVT & VT,SelectionDAG & DAG) const getSplitDestVTs() argument
1776 EVT VT = Op.getValueType(); SplitVectorLoad() local
1836 EVT VT = Op.getValueType(); WidenOrSplitVectorLoad() local
1871 EVT VT = Val.getValueType(); SplitVectorStore() local
1914 EVT VT = Op.getValueType(); LowerDIVREM24() local
2030 EVT VT = Op.getValueType(); LowerUDIVREM64() local
2243 EVT VT = Op.getValueType(); LowerUDIVREM() local
2298 EVT VT = Op.getValueType(); LowerSDIVREM() local
2358 EVT VT = Op.getValueType(); LowerFREM() local
2494 auto VT = Op.getValueType(); LowerFRINT() local
2507 EVT VT = Op.getValueType(); LowerFROUND() local
2601 EVT VT = Src.getValueType(); getIsLtSmallestNormal() local
2618 EVT VT = Src.getValueType(); getIsFinite() local
2637 MVT VT = MVT::f32; getScaledLogInput() local
2663 EVT VT = Op.getValueType(); LowerFLOG2() local
2690 getMad(SelectionDAG & DAG,const SDLoc & SL,EVT VT,SDValue X,SDValue Y,SDValue C,SDNodeFlags Flags=SDNodeFlags ()) getMad() argument
2699 EVT VT = Op.getValueType(); LowerFLOGCommon() local
2802 EVT VT = Src.getValueType(); LowerFLOGUnsafe() local
2843 EVT VT = Op.getValueType(); lowerFEXP2() local
2892 EVT VT = X.getValueType(); lowerFEXPUnsafe() local
2932 const EVT VT = X.getValueType(); lowerFEXP10Unsafe() local
2982 EVT VT = Op.getValueType(); lowerFEXP() local
3673 MVT VT = Op.getSimpleValueType(); LowerSIGN_EXTEND_INREG() local
3702 EVT VT = Op.getValueType(); isI24() local
3814 EVT VT = LN->getMemoryVT(); performLoadCombine() local
3865 EVT VT = SN->getMemoryVT(); performStoreCombine() local
3997 EVT VT = N->getValueType(0); performShlCombine() local
4104 EVT VT = N->getValueType(0); performSrlCombine() local
4150 EVT VT = N->getValueType(0); performTruncateCombine() local
4268 EVT VT = N->getValueType(0); performMulCombine() local
4395 EVT VT = N->getValueType(0); performMulhsCombine() local
4428 EVT VT = N->getValueType(0); performMulhuCombine() local
4463 EVT VT = Op.getValueType(); getFFBX_U32() local
4527 EVT VT = N1.getValueType(); distributeOpThroughSelect() local
4550 EVT VT = N.getValueType(); foldFreeOpFromSelect() local
4629 EVT VT = N->getValueType(0); performSelectCombine() local
4749 EVT VT = N->getValueType(0); performFNegCombine() local
5257 EVT VT = N->getValueType(0); PerformDAGCombine() local
5293 CreateLiveInRegister(SelectionDAG & DAG,const TargetRegisterClass * RC,Register Reg,EVT VT,const SDLoc & SL,bool RawReg) const CreateLiveInRegister() argument
5328 loadStackInputValue(SelectionDAG & DAG,EVT VT,const SDLoc & SL,int64_t Offset) const loadStackInputValue() argument
5364 loadInputValue(SelectionDAG & DAG,const TargetRegisterClass * RC,EVT VT,const SDLoc & SL,const ArgDescriptor & Arg) const loadInputValue() argument
5582 EVT VT = Operand.getValueType(); getSqrtEstimate() local
5598 EVT VT = Operand.getValueType(); getRecipEstimate() local
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