Lines Matching defs:VT
103 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT,
110 VT == MVT::f32 ? Call_F32 :
111 VT == MVT::f64 ? Call_F64 :
112 VT == MVT::f80 ? Call_F80 :
113 VT == MVT::f128 ? Call_F128 :
114 VT == MVT::ppcf128 ? Call_PPCF128 :
456 MVT VT) {
457 if (!VT.isScalarInteger())
459 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
497 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
500 switch (VT.SimpleTy) { \
678 for (MVT VT : {MVT::i2, MVT::i4})
679 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
682 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
683 setTruncStoreAction(AVT, VT, Expand);
684 setLoadExtAction(ISD::EXTLOAD, AVT, VT, Expand);
685 setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand);
690 for (MVT VT : {MVT::i2, MVT::i4}) {
691 setIndexedLoadAction(IM, VT, Expand);
692 setIndexedStoreAction(IM, VT, Expand);
693 setIndexedMaskedLoadAction(IM, VT, Expand);
694 setIndexedMaskedStoreAction(IM, VT, Expand);
698 for (MVT VT : MVT::fp_valuetypes()) {
699 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
701 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote);
702 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT);
707 for (MVT VT : MVT::all_valuetypes()) {
711 setIndexedLoadAction(IM, VT, Expand);
712 setIndexedStoreAction(IM, VT, Expand);
713 setIndexedMaskedLoadAction(IM, VT, Expand);
714 setIndexedMaskedStoreAction(IM, VT, Expand);
718 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
739 VT, Expand);
744 VT, Expand);
749 VT, Expand);
752 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT,
756 setOperationAction({ISD::UCMP, ISD::SCMP}, VT, Expand);
760 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT,
764 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand);
767 setOperationAction(ISD::TRUNCATE_SSAT_S, VT, Expand);
768 setOperationAction(ISD::TRUNCATE_SSAT_U, VT, Expand);
769 setOperationAction(ISD::TRUNCATE_USAT_U, VT, Expand);
772 setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
775 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand);
779 {ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP, ISD::FSINCOS}, VT,
783 if (VT.isVector())
790 VT, Expand);
794 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
798 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand);
808 VT, Expand);
811 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand);
814 setOperationAction(ISD::VECTOR_COMPRESS, VT, Expand);
818 setOperationAction(ISD::SDOPC, VT, Expand);
822 setOperationAction(ISD::VECTOR_FIND_LAST_ACTIVE, VT, Expand);
825 setOperationAction(ISD::GET_FPENV, VT, Expand);
826 setOperationAction(ISD::SET_FPENV, VT, Expand);
827 setOperationAction(ISD::RESET_FPENV, VT, Expand);
874 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
875 setOperationAction(ISD::GET_FPMODE, VT, Expand);
876 setOperationAction(ISD::SET_FPMODE, VT, Expand);
905 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
906 assert(isTypeLegal(VT));
948 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
950 if (VT.isSimple()) {
951 MVT SVT = VT.getSimpleVT();
970 if (!VT.isVector()) {
971 assert(VT.isInteger() && "Float types must be simple");
972 unsigned BitSize = VT.getSizeInBits();
975 EVT NVT = VT.getRoundIntegerType(Context);
976 assert(NVT != VT && "Unable to round integer VT");
986 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
990 ElementCount NumElts = VT.getVectorElementCount();
991 EVT EltVT = VT.getVectorElementType();
1003 if (!VT.isPow2VectorType()) {
1015 if (VT.getVectorElementCount().isScalable())
1018 VT.getHalfNumVectorElementsVT(Context));
1073 if (!VT.isPow2VectorType()) {
1074 EVT NVT = VT.getPow2VectorType(Context);
1078 if (VT.getVectorElementCount() == ElementCount::getScalable(1))
1083 VT.getVectorElementCount().divideCoefficientBy(2));
1087 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1092 ElementCount EC = VT.getVectorElementCount();
1093 MVT EltTy = VT.getVectorElementType();
1099 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1249 MVT VT) const {
1250 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1403 MVT VT = (MVT::SimpleValueType) i;
1404 if (isTypeLegal(VT))
1407 MVT EltVT = VT.getVectorElementType();
1408 ElementCount EC = VT.getVectorElementCount();
1410 bool IsScalable = VT.isScalableVector();
1411 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1429 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1452 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1461 MVT NVT = VT.getPow2VectorType();
1464 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1477 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1484 MVT NVT = VT.getPow2VectorType();
1485 if (NVT == VT) {
1489 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1491 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1493 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1495 ValueTypeActions.setTypeAction(VT, EC.isScalable()
1500 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1524 EVT VT) const {
1525 assert(!VT.isVector() && "No default SetCC type for vectors!");
1538 /// This method returns the number of registers needed, and the VT for each
1539 /// register. It also returns the VT and quantity of the intermediate values
1542 EVT VT, EVT &IntermediateVT,
1545 ElementCount EltCnt = VT.getVectorElementCount();
1552 LegalizeTypeAction TA = getTypeAction(Context, VT);
1555 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1565 EVT EltTy = VT.getVectorElementType();
1573 EVT PartVT = VT;
1575 // Iterate until we've found a legal (part) type to hold VT.
1586 divideCeil(VT.getVectorElementCount().getKnownMinValue(),
1671 EVT VT = ValueVTs[j];
1679 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1680 VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind);
1683 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1685 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1699 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1709 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1716 Type *Ty = VT.getTypeForEVT(Context);
1717 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1725 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1729 LLVMContext &Context, const DataLayout &DL, EVT VT,
1731 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(),
1736 const DataLayout &DL, EVT VT,
1740 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1745 const DataLayout &DL, EVT VT,
1748 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1756 EVT VT = getApproximateEVTForLLT(Ty, Context);
1757 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
2047 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2048 std::string Name = VT.isVector() ? "vec-" : "";
2053 if (VT.getScalarType() == MVT::f64) {
2055 } else if (VT.getScalarType() == MVT::f16) {
2058 assert(VT.getScalarType() == MVT::f32 &&
2092 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2125 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2152 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2180 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2198 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT,
2200 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2203 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT,
2205 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2208 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT,
2210 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2213 int TargetLoweringBase::getDivRefinementSteps(EVT VT,
2215 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));