Lines Matching defs:VT
726 MVT VT = Node->getSimpleValueType(0);
727 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
761 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
762 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
767 Res = DAG.getNode(ISD::VP_FP_ROUND, dl, VT, Res,
770 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res,
774 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);
784 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType();
785 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
786 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() &&
822 MVT VT = Node->getSimpleValueType(0);
823 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
825 assert(NVT.getVectorNumElements() == VT.getVectorNumElements() &&
858 DAG.getValueType(VT.getScalarType()));
859 Promoted = DAG.getNode(ISD::TRUNCATE, dl, VT, Promoted);
1271 EVT VT = Node->getValueType(0);
1278 assert(VT.isVector() && !Mask.getValueType().isVector()
1289 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
1290 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
1291 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
1292 TLI.getOperationAction(VT.isFixedLengthVector() ? ISD::BUILD_VECTOR
1294 VT) == TargetLowering::Expand)
1298 EVT MaskTy = VT.changeVectorElementTypeToInteger();
1324 EVT VT = Node->getValueType(0);
1327 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
1328 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
1334 unsigned BW = VT.getScalarSizeInBits();
1336 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
1338 SDValue Op = DAG.getNode(ISD::SHL, DL, VT, Node->getOperand(0), ShiftSz);
1339 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
1346 EVT VT = Node->getValueType(0);
1347 int NumElements = VT.getVectorNumElements();
1352 // *_EXTEND_VECTOR_INREG SrcVT can be smaller than VT - so insert the vector
1354 if (SrcVT.bitsLE(VT)) {
1355 assert((VT.getSizeInBits() % SrcVT.getScalarSizeInBits()) == 0 &&
1357 NumSrcElements = VT.getSizeInBits() / SrcVT.getScalarSizeInBits();
1375 ISD::BITCAST, DL, VT,
1381 EVT VT = Node->getValueType(0);
1387 SDValue Op = DAG.getNode(ISD::ANY_EXTEND_VECTOR_INREG, DL, VT, Src);
1392 unsigned EltWidth = VT.getScalarSizeInBits();
1394 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
1395 return DAG.getNode(ISD::SRA, DL, VT,
1396 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
1405 EVT VT = Node->getValueType(0);
1406 int NumElements = VT.getVectorNumElements();
1411 // *_EXTEND_VECTOR_INREG SrcVT can be smaller than VT - so insert the vector
1413 if (SrcVT.bitsLE(VT)) {
1414 assert((VT.getSizeInBits() % SrcVT.getScalarSizeInBits()) == 0 &&
1416 NumSrcElements = VT.getSizeInBits() / SrcVT.getScalarSizeInBits();
1435 return DAG.getNode(ISD::BITCAST, DL, VT,
1439 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) {
1440 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
1441 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
1447 EVT VT = Node->getValueType(0);
1450 if (VT.isScalableVector())
1455 createBSWAPShuffleMask(VT, ShuffleMask);
1463 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
1468 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
1469 TLI.isOperationLegalOrCustom(ISD::SRL, VT) &&
1470 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) &&
1471 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
1479 EVT VT = Node->getValueType(0);
1482 if (VT.isScalableVector())
1486 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
1492 unsigned ScalarSizeInBits = VT.getScalarSizeInBits();
1495 createBSWAPShuffleMask(VT, BSWAPMask);
1509 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
1516 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
1517 TLI.isOperationLegalOrCustom(ISD::SRL, VT) &&
1518 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) &&
1519 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
1535 EVT VT = Mask.getValueType();
1541 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
1542 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
1543 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand)
1559 if (VT.getSizeInBits() != Op1.getValueSizeInBits())
1565 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
1566 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
1568 SDValue NotMask = DAG.getNOT(DL, Mask, VT);
1570 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
1571 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
1572 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
1586 EVT VT = Mask.getValueType();
1590 if (TLI.getOperationAction(ISD::VP_AND, VT) == TargetLowering::Expand ||
1591 TLI.getOperationAction(ISD::VP_XOR, VT) == TargetLowering::Expand ||
1592 TLI.getOperationAction(ISD::VP_OR, VT) == TargetLowering::Expand)
1599 SDValue Ones = DAG.getAllOnesConstant(DL, VT);
1600 SDValue NotMask = DAG.getNode(ISD::VP_XOR, DL, VT, Mask, Ones, Ones, EVL);
1602 Op1 = DAG.getNode(ISD::VP_AND, DL, VT, Op1, Mask, Ones, EVL);
1603 Op2 = DAG.getNode(ISD::VP_AND, DL, VT, Op2, NotMask, Ones, EVL);
1604 return DAG.getNode(ISD::VP_OR, DL, VT, Op1, Op2, Ones, EVL);
1650 EVT VT = Node->getValueType(0);
1654 if (!TLI.isOperationLegalOrCustom(DivOpc, VT) ||
1655 !TLI.isOperationLegalOrCustom(ISD::VP_MUL, VT) ||
1656 !TLI.isOperationLegalOrCustom(ISD::VP_SUB, VT))
1667 SDValue Div = DAG.getNode(DivOpc, DL, VT, Dividend, Divisor, Mask, EVL);
1668 SDValue Mul = DAG.getNode(ISD::VP_MUL, DL, VT, Divisor, Div, Mask, EVL);
1669 return DAG.getNode(ISD::VP_SUB, DL, VT, Dividend, Mul, Mask, EVL);
1673 EVT VT = Node->getValueType(0);
1674 EVT IntVT = VT.changeVectorElementTypeToInteger();
1687 return DAG.getNode(ISD::BITCAST, DL, VT, Xor);
1691 EVT VT = Node->getValueType(0);
1692 EVT IntVT = VT.changeVectorElementTypeToInteger();
1706 return DAG.getNode(ISD::BITCAST, DL, VT, ClearSign);
1710 EVT VT = Node->getValueType(0);
1712 if (VT != Node->getOperand(1).getValueType())
1715 EVT IntVT = VT.changeVectorElementTypeToInteger();
1740 return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);
1876 EVT VT = Node->getValueType(0);
1877 EVT IntVT = VT.changeVectorElementTypeToInteger();
1883 if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
1884 !VT.isScalableVector())
1892 return DAG.getNode(ISD::BITCAST, DL, VT, Xor);
1896 EVT VT = Node->getValueType(0);
1897 EVT IntVT = VT.changeVectorElementTypeToInteger();
1903 if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
1904 !VT.isScalableVector())
1912 return DAG.getNode(ISD::BITCAST, DL, VT, ClearedSign);
1916 EVT VT = Node->getValueType(0);
1917 EVT IntVT = VT.changeVectorElementTypeToInteger();
1919 if (VT != Node->getOperand(1).getValueType() ||
1925 if (!TLI.isOperationLegalOrCustomOrPromote(ISD::FSUB, VT) &&
1926 !VT.isScalableVector())
1944 return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);
1952 EVT VT = Node->getValueType(0);
1953 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
1954 TLI.isOperationLegalOrCustom(ISD::FADD, VT))
2033 EVT VT = Node->getValueType(0);
2035 DAG.getNode(ISD::SELECT_CC, dl, VT, LHS, RHS,
2036 DAG.getBoolConstant(true, dl, VT, LHS.getValueType()),
2037 DAG.getBoolConstant(false, dl, VT, LHS.getValueType()), CC);
2128 EVT VT = Node->getValueType(0);
2129 ElementCount VL = VT.getVectorElementCount();
2141 Type *Ty = VT.getTypeForEVT(*Ctx);
2147 assert(Node->getOperand(i).getValueType() == VT &&
2178 EVT MaskVT = TLI.getSetCCResultType(DAG.getDataLayout(), *Ctx, VT);
2179 Entry.Node = DAG.getBoolConstant(true, DL, MaskVT, VT);
2224 EVT VT = Node->getValueType(0);
2225 EVT EltVT = VT.getVectorElementType();
2226 unsigned NumElems = VT.getVectorNumElements();
2275 SDValue Result = DAG.getBuildVector(VT, dl, OpValues);
2283 EVT VT = Node->getValueType(0);
2284 unsigned NumElems = VT.getVectorNumElements();
2285 EVT EltVT = VT.getVectorElementType();
2303 DAG.getBoolConstant(true, dl, EltVT, VT),
2306 return DAG.getBuildVector(VT, dl, Ops);