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Searched defs:V0 (Results 1 – 25 of 38) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp191 SDValue V0 = N->getOperand(i + 1); selectInlineAsm() local
376 createGPRPairNode(EVT VT,SDValue V0,SDValue V1) createGPRPairNode() argument
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp84 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() local
H A DMips16ISelDAGToDAG.cpp75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); in initGlobalBaseReg() local
/freebsd-src/lib/msun/src/
H A De_j1f.c93 static const float V0[5] = { variable
H A De_j1.c130 static const double V0[5] = { variable
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp226 SDValue V0 = N->getOperand(i+1); tryInlineAsm() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1847 createGPRPairNode(EVT VT,SDValue V0,SDValue V1) createGPRPairNode() argument
1858 createSRegPairNode(EVT VT,SDValue V0,SDValue V1) createSRegPairNode() argument
1869 createDRegPairNode(EVT VT,SDValue V0,SDValue V1) createDRegPairNode() argument
1880 createQRegPairNode(EVT VT,SDValue V0,SDValue V1) createQRegPairNode() argument
1891 createQuadSRegsNode(EVT VT,SDValue V0,SDValue V1,SDValue V2,SDValue V3) createQuadSRegsNode() argument
1906 createQuadDRegsNode(EVT VT,SDValue V0,SDValue V1,SDValue V2,SDValue V3) createQuadDRegsNode() argument
1921 createQuadQRegsNode(EVT VT,SDValue V0,SDValue V1,SDValue V2,SDValue V3) createQuadQRegsNode() argument
2312 SDValue V0 = N->getOperand(Vec0Idx + 0); SelectVST() local
2368 SDValue V0 = N->getOperand(Vec0Idx + 0); SelectVST() local
2487 SDValue V0 = N->getOperand(Vec0Idx + 0); SelectVLDSTLane() local
5779 SDValue V0 = N->getOperand(i+1); tryInlineAsm() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVectorCombine.cpp529 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); foldExtExtCmp() local
547 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); foldExtExtBinop() local
573 Value *V0, *V1; foldExtractExtract() local
889 Value *V0 = nullptr, *V1 = nullptr; scalarizeBinopOrCmp() local
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/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp391 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local
469 Value *V0 = I->getOperand(0); in simplify() local
2291 Value *V0, *V1; visitSub() local
2942 Value *A0, *A1, *V0, *V1; visitFSub() local
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H A DInstCombineVectorOps.cpp84 Value *V0, *V1; in cheapToScalarize() local
2585 Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); foldShuffleWithInsert() local
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H A DInstCombineCalls.cpp2632 Value *V0 = Builder.CreateIntCast(CV0, NewVT, /*isSigned=*/!Zext); visitCallInst() local
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp5531 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_VECTOR_SPLICE() local
5541 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE() local
5659 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_VECTOR_REVERSE() local
5672 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_VECTOR_SHUFFLE() local
5854 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_INSERT_VECTOR_ELT() local
5882 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntOp_EXTRACT_VECTOR_ELT() local
5898 SDValue V0 = N->getOperand(0); PromoteIntOp_INSERT_SUBVECTOR() local
5911 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntOp_EXTRACT_SUBVECTOR() local
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/freebsd-src/crypto/openssl/crypto/aria/
H A Daria.c54 #define MAKE_U32(V0, V1, V2, V3) ( \ argument
/freebsd-src/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp132 Value *V0 = I->getOperand(0); in XorOpnd() local
1073 Value *V0 = Sub->getOperand(0); ShouldBreakUpSubtract() local
H A DConstraintElimination.cpp1628 Value *V0 = B.isConditionFact() ? B.Cond.Op0 : B.Inst->getOperand(0); eliminateConstraints() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp1370 SDValue V0, V1; in insertHvxSubvectorReg() local
1621 SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG); in LowerHvxBuildVector() local
1732 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors() local
3530 SDValue V0 = Op.getOperand(0); in combineConcatVectorsBeforeLegal() local
H A DHexagonISelDAGToDAG.cpp2216 SDValue V0 = L0.Value; balanceSubTree() local
2274 SDValue V0 = NewRoot.getOperand(0); balanceSubTree() local
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H A DHexagonLoopIdiomRecognition.cpp1767 uint32_t V0 = C0->getZExtValue(); setupPostSimplifier() local
H A DHexagonISelDAGToDAGHVX.cpp2831 SDValue V0 = N->getOperand(0); in ppHvxShuffleOfShuffle() local
/freebsd-src/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp945 Value *V0 = ResList[i], *V1 = ResList[i + 1]; concatenateVectors() local
/freebsd-src/sys/geom/raid/
H A Dmd_ddf.h267 uint8_t V0[32]; member
/freebsd-src/contrib/llvm-project/clang/lib/Headers/
H A Dhexagon_types.h2549 HVX_Vector V0(void) { return HEXAGON_HVX_GET_V0(data); }; in V0() function
2558 HVX_Vect V0(HVX_Vector v) { return HVX_Vect(HEXAGON_HVX_PUT_V0(data, v)); }; in V0() function
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3547 SDValue V0 = DAG.getSelectCC(DL, VLow3, DAG.getConstant(3, DL, MVT::i32), LowerFP_TO_FP16() local
5219 APFloat V0 = FTZ(N0CFP->getValueAPF()); PerformDAGCombine() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp2061 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0)); EmitTest() local
/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1582 SDValue V0 = CurDAG->getRegister(RISCV::V0, VT); Select() local
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