Lines Matching defs:V0
337 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
338 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
339 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
340 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
343 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
344 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
345 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1853 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1854 SDLoc dl(V0.getNode());
1859 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1864 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1865 SDLoc dl(V0.getNode());
1870 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1875 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1876 SDLoc dl(V0.getNode());
1881 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1886 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1887 SDLoc dl(V0.getNode());
1892 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1897 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1899 SDLoc dl(V0.getNode());
1906 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1912 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1914 SDLoc dl(V0.getNode());
1921 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1927 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1929 SDLoc dl(V0.getNode());
1936 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
2318 SDValue V0 = N->getOperand(Vec0Idx + 0);
2321 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2329 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2374 SDValue V0 = N->getOperand(Vec0Idx + 0);
2380 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2493 SDValue V0 = N->getOperand(Vec0Idx + 0);
2497 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2499 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2506 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2508 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
5780 SDValue V0 = N->getOperand(i+1);
5782 Register Reg0 = cast<RegisterSDNode>(V0)->getReg();