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Searched defs:UseIdx (Results 1 – 25 of 27) sorted by relevance

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/llvm-project/llvm/include/llvm/MC/
H A DMCInstrItineraries.h187 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding()
210 unsigned UseIdx) const { in getOperandLatency()
H A DMCSubtargetInfo.h184 getReadAdvanceCycles(const MCSchedClassDesc * SC,unsigned UseIdx,unsigned WriteResID) getReadAdvanceCycles() argument
H A DMCSchedule.h104 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by member
/llvm-project/llvm/lib/IR/
H A DAbstractCallSite.cpp100 unsigned UseIdx = CB->getArgOperandNo(U); in AbstractCallSite() local
/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp216 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency() local
162 unsigned UseIdx = 0; findUseIdx() local
H A DLiveIntervalCalc.cpp171 SlotIndex UseIdx; extendToUses() local
H A DRegisterCoalescer.cpp886 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI); removeCopyByCommutingDef() local
936 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true); removeCopyByCommutingDef() local
1228 SlotIndex UseIdx = LIS->getInstructionIndex(MI); removePartialRedundancy() local
1756 SlotIndex UseIdx = LIS->getInstructionIndex(MI); eliminateUndefCopy() local
1790 addUndefFlag(const LiveInterval & Int,SlotIndex UseIdx,MachineOperand & MO,unsigned SubRegIdx) addUndefFlag() argument
1829 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true); updateRegDefsUses() local
1887 SlotIndex UseIdx = MIIdx.getRegSlot(true); updateRegDefsUses() local
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H A DLiveRangeEdit.cpp159 SlotIndex UseIdx, boo in canRematerializeAt() argument
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H A DMachineCopyPropagation.cpp555 isBackwardPropagatableRegClassCopy(const MachineInstr & Copy,const MachineInstr & UseI,unsigned UseIdx) isBackwardPropagatableRegClassCopy() argument
574 isForwardableRegClassCopy(const MachineInstr & Copy,const MachineInstr & UseI,unsigned UseIdx) isForwardableRegClassCopy() argument
H A DMachineCombiner.cpp234 InstrPtr, UseIdx); in getDepth() local
H A DMachineVerifier.cpp2652 checkLivenessAtUse(const MachineOperand * MO,unsigned MONum,SlotIndex UseIdx,const LiveRange & LR,Register VRegOrUnit,LaneBitmask LaneMask) checkLivenessAtUse() argument
2767 SlotIndex UseIdx; checkLiveness() local
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H A DInlineSpiller.cpp629 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); reMaterializeFor() local
H A DSplitKit.cpp593 defFromParent(unsigned RegIdx,const VNInfo * ParentVNI,SlotIndex UseIdx,MachineBasicBlock & MBB,MachineBasicBlock::iterator I) defFromParent() argument
H A DTwoAddressInstructionPass.cpp1630 SlotIndex UseIdx = LIS->getInstructionIndex(*MI); processTiedPairs() local
H A DMachineInstr.cpp1163 tieOperands(unsigned DefIdx,unsigned UseIdx) tieOperands() argument
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp680 int UseIdx = SwapMap[&UseMI]; recordUnoptimizableWebs() local
746 int UseIdx = SwapMap[&UseMI]; recordUnoptimizableWebs() local
788 int UseIdx = SwapMap[&UseMI]; markSwapsForRemoval() local
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H A DPPCInstrInfo.h345 unsigned UseIdx) const override; in getOperandLatency() argument
/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp702 unsigned UseIdx; foldImmediate() local
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp470 int UseIdx = -1; adjustSchedDependency() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3953 getVSTMUseCycle(const InstrItineraryData * ItinData,const MCInstrDesc & UseMCID,unsigned UseClass,unsigned UseIdx,unsigned UseAlign) const getVSTMUseCycle() argument
3992 getSTMUseCycle(const InstrItineraryData * ItinData,const MCInstrDesc & UseMCID,unsigned UseClass,unsigned UseIdx,unsigned UseAlign) const getSTMUseCycle() argument
4020 getOperandLatency(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefIdx,unsigned DefAlign,const MCInstrDesc & UseMCID,unsigned UseIdx,unsigned UseAlign) const getOperandLatency() argument
4155 getBundledUseMI(const TargetRegisterInfo * TRI,const MachineInstr & MI,unsigned Reg,unsigned & UseIdx,unsigned & Dist) getBundledUseMI() argument
4401 getOperandLatencyImpl(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MCInstrDesc & DefMCID,unsigned DefAdj,const MachineOperand & DefMO,unsigned Reg,const MachineInstr & UseMI,unsigned UseIdx,const MCInstrDesc & UseMCID,unsigned UseAdj) const getOperandLatencyImpl() argument
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/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp1391 unsigned UseIdx = GroupIdx.back() + 1; EmitSpecialNode() local
/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1266 for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx; GenSchedClassTables() local
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp707 unsigned UseIdx; in foldImmediate() local
/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1814 hasHighOperandLatency(const TargetSchedModel & SchedModel,const MachineRegisterInfo * MRI,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) hasHighOperandLatency() argument
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp3161 SlotIndex UseIdx = LIS->getInstructionIndex(Use); findReachingDef() local

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