Lines Matching defs:UseIdx

3969                                   unsigned UseIdx, unsigned UseAlign) const {
3970   int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3972     return ItinData->getOperandCycle(UseClass, UseIdx);
4008                                  unsigned UseIdx, unsigned UseAlign) const {
4009   int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
4011     return ItinData->getOperandCycle(UseClass, UseIdx);
4036     unsigned UseIdx, unsigned UseAlign) const {
4040   if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
4041     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
4091     UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
4100     UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4118     UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
4135                                           UseClass, UseIdx))
4138                                                UseClass, UseIdx)) {
4171                                            unsigned &UseIdx, unsigned &Dist) {
4194   UseIdx = Idx;
4381     unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4403         getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
4410       Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
4417     unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
4444   if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4456       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4476                                     SDNode *UseNode, unsigned UseIdx) const {
4506       ItinData, DefMCID, DefIdx, DefAlign, UseMCID, UseIdx, UseAlign);
4825                                              unsigned UseIdx) const {
4834       SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);