| /llvm-project/llvm/lib/CodeGen/ |
| H A D | IntrinsicLowering.cpp | 73 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
101 Value* Tmp3 = Builder.CreateLShr(V, in LowerBSWAP() local
|
| /llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | IntegerDivision.cpp | 125 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode() local
262 Value *Tmp3 = Builder.CreateLShr(Dividend, SR_1); in generateUnsignedDivisionCode() local
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4189 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; matchBEXTRFromAndImm() local
4226 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; emitPCMPISTR() local
4259 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; emitPCMPESTR() local
4552 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; matchVPTERNLOG() local
4938 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; tryVPTESTM() local
5514 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
5567 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
5653 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
5787 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
5795 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain; Select() local
6158 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
[all...] |
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1740 SDValue Tmp3 = Node->getOperand(2); ExpandDYNAMIC_STACKALLOC() local
3057 SDValue Tmp1, Tmp2, Tmp3, Tmp4; ExpandNode() local
5081 SDValue Tmp1, Tmp2, Tmp3, Tmp4; PromoteNode() local
[all...] |
| H A D | TargetLowering.cpp | 8075 SDValue Tmp2, Tmp3; expandShiftParts() local
8862 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; expandVPCTPOP() local
9302 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; expandBSWAP() local
9362 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; expandVPBSWAP() local
9434 SDValue Tmp, Tmp2, Tmp3; expandBITREVERSE() local
9499 SDValue Tmp, Tmp2, Tmp3; expandVPBITREVERSE() local
[all...] |
| H A D | LegalizeFloatTypes.cpp | 2014 SDValue Tmp1, Tmp2, Tmp3, OutputChain; FloatExpandSetCCOperands() local
|
| /llvm-project/llvm/unittests/IR/ |
| H A D | PassManagerTest.cpp | 380 auto Tmp3 = PA1; in TEST() local
|
| /llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprComplex.cpp | 1080 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd EmitBinDiv() local
|
| /llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2119 Register Tmp3 = MRI.createVirtualRegister(RC); prepareSymbol() local
|
| /llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 3094 SDValue Tmp3 = ST->getValue(); LowerSTOREi1() local
|
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 2335 SDValue Tmp3 = lowerVAARG() local
|
| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 2466 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, IntTy, Tmp2, Rup); emitHvxShiftRightRnd() local
|
| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 9127 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); LowerSHL_PARTS() local
9156 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); LowerSRL_PARTS() local
9184 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); LowerSRA_PARTS() local
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 3955 SDValue Tmp3 = Op.getOperand(2); lowerDYNAMIC_STACKALLOCImpl() local
|