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Searched defs:Tmp1 (Results 1 – 25 of 30) sorted by relevance

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/llvm-project/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp63 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
77 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), in LowerBSWAP() local
107 Value* Tmp1 = Builder.CreateLShr(V, in LowerBSWAP() local
/llvm-project/clang/test/CodeGenCXX/
H A Dmatrix-type.cpp52 char Tmp1; member
93 int Tmp1; member in MatrixClass
119 int Tmp1; member in MatrixClassTemplate
/llvm-project/clang/test/CodeGen/
H A Dmatrix-type.c127 char Tmp1; member
/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp122 Value *Tmp1 = Builder.CreateAShr(Divisor, Shift); in generateSignedDivisionCode() local
235 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode() local
/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2030 Register Tmp1 = MRI.createVirtualRegister(RC); prepareMBB() local
2094 Register Tmp1 = MRI.createVirtualRegister(RC); prepareSymbol() local
2112 Register Tmp1 = MRI.createVirtualRegister(RC); prepareSymbol() local
2137 Register Tmp1 = MRI.createVirtualRegister(RC); prepareSymbol() local
2523 Register Tmp1 = MRI.createVirtualRegister(RC); emitSjLjDispatchBlock() local
2568 Register Tmp1 = MRI.createVirtualRegister(RC); emitSjLjDispatchBlock() local
2594 Register Tmp1 = MRI.createVirtualRegister(RC); emitSjLjDispatchBlock() local
[all...]
/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp4189 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; matchBEXTRFromAndImm() local
4226 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; emitPCMPISTR() local
4259 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; emitPCMPESTR() local
4552 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; matchVPTERNLOG() local
4938 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; tryVPTESTM() local
5514 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
5567 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
5653 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
5787 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
5795 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain; Select() local
6158 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; Select() local
[all...]
/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2462 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); LowerShiftRightParts() local
2522 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); LowerShiftLeftParts() local
2828 SDValue Tmp1 = Node->getOperand(0); LowerVAARG() local
3092 SDValue Tmp1 = ST->getChain(); LowerSTOREi1() local
[all...]
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1738 SDValue Tmp1 = SDValue(Node, 0); ExpandDYNAMIC_STACKALLOC() local
2794 SDValue Tmp1; ExpandLegalINT_TO_FP() local
3057 SDValue Tmp1, Tmp2, Tmp3, Tmp4; ExpandNode() local
5081 SDValue Tmp1, Tmp2, Tmp3, Tmp4; PromoteNode() local
[all...]
H A DTargetLowering.cpp8071 SDValue Tmp1 = IsSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, expandShiftParts() local
8862 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5; expandVPCTPOP() local
9302 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; expandBSWAP() local
9362 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; expandVPBSWAP() local
[all...]
H A DLegalizeFloatTypes.cpp2014 SDValue Tmp1, Tmp2, Tmp3, OutputChain; FloatExpandSetCCOperands() local
[all...]
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp687 auto *Tmp1 = MF.getMachineMemOperand(Ptr, F, 4 /*size*/, A); in splitMemRef() local
H A DHexagonHardwareLoops.cpp1859 SmallVector<MachineOperand,2> Tmp1; createPreheaderForLoop() local
H A DHexagonISelLoweringHVX.cpp2464 SDValue Tmp1 = DAG.getNode(ShRight, dl, IntTy, Inp, AmtM1); emitHvxShiftRightRnd() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp1482 Value *Tmp1 = Builder.CreateMul(TIdY, TCntZ, "", true, true); tryPromoteAllocaToLDS() local
H A DAMDGPUISelLowering.cpp2450 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); LowerFTRUNC() local
2469 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign); LowerFROUNDEVEN() local
5840 unsigned Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), Depth + 1); ComputeNumSignBitsForTargetNode() local
5879 unsigned Tmp1 = Analysis.computeNumSignBits(Src1, DemandedElts, Depth + 1); computeNumSignBitsForTargetInstr() local
[all...]
H A DAMDGPULegalizerInfo.cpp2435 auto Tmp1 = B.buildFAdd(Ty, Src, CopySign); legalizeFroundeven() local
2549 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); legalizeIntrinsicTrunc() local
4864 auto Tmp1 = B.buildFMA(ResTy, NegY, R, One); legalizeFastUnsafeFDIV64() local
/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DCheckerManager.cpp123 ExplodedNodeSet Tmp1, Tmp2; expandGraphWithCheckers() local
/llvm-project/clang/lib/CodeGen/
H A DCGExprComplex.cpp1078 llvm::Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c EmitBinDiv() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6268 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); Select() local
6282 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); Select() local
H A DPPCISelLowering.cpp9124 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, LowerSHL_PARTS() local
9153 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, LowerSRL_PARTS() local
9181 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, LowerSRA_PARTS() local
/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp503 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; LowerFPToInt() local
/llvm-project/llvm/lib/Support/
H A DAPInt.cpp722 uint64_t Tmp1 = llvm::byteswap<uint64_t>(U.VAL); byteSwap() local
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp3209 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); LowerUMULO_SMULO() local
/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1971 SDValue Tmp1, Tmp2; ReplaceNodeResults() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6055 SDValue Tmp1 = Op.getOperand(1); LowerFCOPYSIGN() local
6353 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); LowerShiftRightParts() local
6395 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); LowerShiftLeftParts() local
[all...]

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