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Searched defs:TempReg (Results 1 – 9 of 9) sorted by relevance

/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp648 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp() local
391 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); materializeFP() local
422 Register TempReg = createResultReg(RC); materializeGV() local
654 Register TempReg = createResultReg(&Mips::GPR32RegClass); emitCmp() local
666 Register TempReg = createResultReg(&Mips::GPR32RegClass); emitCmp() local
672 Register TempReg = createResultReg(&Mips::GPR32RegClass); emitCmp() local
684 Register TempReg = createResultReg(&Mips::GPR32RegClass); emitCmp() local
690 Register TempReg = createResultReg(&Mips::GPR32RegClass); emitCmp() local
1053 Register TempReg = createResultReg(RC); selectSelect() local
1119 Register TempReg = createResultReg(&Mips::FGR32RegClass); selectFPToInt() local
1603 unsigned TempReg[3]; fastLowerIntrinsicCall() local
1618 Register TempReg = createResultReg(&Mips::GPR32RegClass); fastLowerIntrinsicCall() local
1624 unsigned TempReg[8]; fastLowerIntrinsicCall() local
1836 Register TempReg = createResultReg(&Mips::GPR32RegClass); emitIntSExt32r1() local
1971 Register TempReg = createResultReg(&Mips::GPR32RegClass); selectShift() local
2097 Register TempReg = createResultReg(&Mips::GPR32RegClass); getRegEnsuringSimpleIntegerWidening() local
2107 unsigned TempReg = simplifyAddress() local
[all...]
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp659 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg emitPrologue() local
1294 __anon633ee97d0702(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int64_t Imm, Register &TempReg) inlineStackProbe() argument
1351 __anon633ee97d0902(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register ScratchReg, Register TempReg) inlineStackProbe() argument
1577 Register TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg emitEpilogue() local
[all...]
H A DPPCISelDAGToDAG.cpp485 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); in INITIALIZE_PASS() local
H A DPPCISelLowering.cpp12779 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); emitProbedAlloca() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp1815 Register TempReg = MI.getOperand(1).getReg(); ExpandCMP_SWAP() local
1945 Register TempReg = MI.getOperand(1).getReg(); ExpandCMP_SWAP_64() local
H A DARMFastISel.cpp2972 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass); ARMLowerPICELF() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetMachine.cpp1547 Register TempReg; parseMachineFunctionInfo() local
/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp922 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D; LowerKCFI_CHECK() local
/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp3403 unsigned TempReg = Inst.getOperand(1).getReg(); validateInstruction() local