Lines Matching defs:TempReg

389     unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
390     emitInst(Mips::MTC1, DestReg).addReg(TempReg);
420     Register TempReg = createResultReg(RC);
421     emitInst(Mips::ADDiu, TempReg)
424     DestReg = TempReg;
646     Register TempReg = createResultReg(&Mips::GPR32RegClass);
647     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
648     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
652     Register TempReg = createResultReg(&Mips::GPR32RegClass);
653     emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
654     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
664     Register TempReg = createResultReg(&Mips::GPR32RegClass);
665     emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
666     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
670     Register TempReg = createResultReg(&Mips::GPR32RegClass);
671     emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
672     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
682     Register TempReg = createResultReg(&Mips::GPR32RegClass);
683     emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
684     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
688     Register TempReg = createResultReg(&Mips::GPR32RegClass);
689     emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
690     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
1065   Register TempReg = createResultReg(RC);
1067   if (!ResultReg || !TempReg)
1070   emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1072     .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1131   Register TempReg = createResultReg(&Mips::FGR32RegClass);
1135   emitInst(Opc, TempReg).addReg(SrcReg);
1136   emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1615         unsigned TempReg[3];
1616         for (unsigned &R : TempReg) {
1621         emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1622         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1623         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[1]).addImm(0xFF);
1624         emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]);
1630         Register TempReg = createResultReg(&Mips::GPR32RegClass);
1631         emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1632         emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1636         unsigned TempReg[8];
1637         for (unsigned &R : TempReg) {
1643         emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1644         emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1645         emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1646         emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1648         emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1649         emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1651         emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1652         emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1653         emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1848   Register TempReg = createResultReg(&Mips::GPR32RegClass);
1849   emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1850   emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1983     Register TempReg = createResultReg(&Mips::GPR32RegClass);
1984     if (!TempReg)
1989     if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1992     Op0Reg = TempReg;
2109     Register TempReg = createResultReg(&Mips::GPR32RegClass);
2110     if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
2112     VReg = TempReg;
2119     unsigned TempReg =
2122     emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());