| /llvm-project/llvm/unittests/CodeGen/ |
| H A D | AArch64SelectionDAGTest.cpp | 182 TargetLowering::TargetLoweringOpt TLO(*DAG, false, false); TEST_F() local
209 TargetLowering::TargetLoweringOpt TLO(*DAG, false, false); TEST_F() local
236 TargetLowering::TargetLoweringOpt TLO(*DAG, false, false); TEST_F() local
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| /llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1510 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), PerformDAGCombine() local
1526 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), PerformDAGCombine() local
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 623 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), SimplifyDemandedBits() local
639 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), SimplifyDemandedBits() local
654 SimplifyDemandedBits(SDValue Op,const APInt & DemandedBits,KnownBits & Known,TargetLoweringOpt & TLO,unsigned Depth,bool AssumeSingleUse) const SimplifyDemandedBits() argument
955 combineShiftToAVG(SDValue Op,TargetLowering::TargetLoweringOpt & TLO,const TargetLowering & TLI,const APInt & DemandedBits,const APInt & DemandedElts,unsigned Depth) combineShiftToAVG() argument
1103 SimplifyDemandedBits(SDValue Op,const APInt & OriginalDemandedBits,const APInt & OriginalDemandedElts,KnownBits & Known,TargetLoweringOpt & TLO,unsigned Depth,bool AssumeSingleUse) const SimplifyDemandedBits() argument
2969 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), SimplifyDemandedVectorElts() local
3033 SimplifyDemandedVectorElts(SDValue Op,const APInt & OriginalDemandedElts,APInt & KnownUndef,APInt & KnownZero,TargetLoweringOpt & TLO,unsigned Depth,bool AssumeSingleUse) const SimplifyDemandedVectorElts() argument
3771 SimplifyDemandedVectorEltsForTargetNode(SDValue Op,const APInt & DemandedElts,APInt & KnownUndef,APInt & KnownZero,TargetLoweringOpt & TLO,unsigned Depth) const SimplifyDemandedVectorEltsForTargetNode() argument
3783 SimplifyDemandedBitsForTargetNode(SDValue Op,const APInt & DemandedBits,const APInt & DemandedElts,KnownBits & Known,TargetLoweringOpt & TLO,unsigned Depth) const SimplifyDemandedBitsForTargetNode() argument
[all...] |
| H A D | DAGCombiner.cpp | 925 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & TLO) CommitTargetLoweringOpt() argument
1355 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & TLO) CommitTargetLoweringOpt() argument
1376 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); SimplifyDemandedBits() local
1395 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); SimplifyDemandedVectorElts() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3980 targetShrinkDemandedConstant(SDValue Op,const APInt & DemandedBits,const APInt & DemandedElts,TargetLoweringOpt & TLO) targetShrinkDemandedConstant() argument
4077 shouldSimplifyDemandedVectorElts(SDValue Op,const TargetLoweringOpt & TLO) shouldSimplifyDemandedVectorElts() argument
[all...] |
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 5230 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), PerformDAGCombine() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2151 optimizeLogicalImm(SDValue Op,unsigned Size,uint64_t Imm,const APInt & Demanded,TargetLowering::TargetLoweringOpt & TLO,unsigned NewOpc) optimizeLogicalImm() argument
22333 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), performTBISimplification() local
28174 SimplifyDemandedBitsForTargetNode(SDValue Op,const APInt & OriginalDemandedBits,const APInt & OriginalDemandedElts,KnownBits & Known,TargetLoweringOpt & TLO,unsigned Depth) const SimplifyDemandedBitsForTargetNode() argument
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| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 41763 SimplifyDemandedVectorEltsForTargetShuffle(SDValue Op,const APInt & DemandedElts,unsigned MaskIndex,TargetLowering::TargetLoweringOpt & TLO,unsigned Depth) const SimplifyDemandedVectorEltsForTargetShuffle() argument
41830 SimplifyDemandedVectorEltsForTargetNode(SDValue Op,const APInt & DemandedElts,APInt & KnownUndef,APInt & KnownZero,TargetLoweringOpt & TLO,unsigned Depth) const SimplifyDemandedVectorEltsForTargetNode() argument
42597 SimplifyDemandedBitsForTargetNode(SDValue Op,const APInt & OriginalDemandedBits,const APInt & OriginalDemandedElts,KnownBits & Known,TargetLoweringOpt & TLO,unsigned Depth) const SimplifyDemandedBitsForTargetNode() argument
45672 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), combineVSelectToBLENDV() local
[all...] |
| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 20294 SimplifyDemandedBitsForTargetNode(SDValue Op,const APInt & OriginalDemandedBits,const APInt & OriginalDemandedElts,KnownBits & Known,TargetLoweringOpt & TLO,unsigned Depth) const SimplifyDemandedBitsForTargetNode() argument
[all...] |