| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1238 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); copyFromSrcRegs() local
1286 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); mergeRead2Pair() local
1415 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); mergeImagePair() local
1451 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); mergeSMemLoadImmPair() local
1484 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); mergeBufferLoadPair() local
1525 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); mergeTBufferLoadPair() local
1611 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); mergeFlatLoadPair() local
[all...] |
| H A D | SIRegisterInfo.cpp | 2907 getCompatibleSubRegClass(const TargetRegisterClass * SuperRC,const TargetRegisterClass * SubRC,unsigned SubIdx) const getCompatibleSubRegClass() argument
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| H A D | SIInstrInfo.cpp | 5652 buildExtractSubReg(MachineBasicBlock::iterator MI,MachineRegisterInfo & MRI,const MachineOperand & SuperReg,const TargetRegisterClass * SuperRC,unsigned SubIdx,const TargetRegisterClass * SubRC) const buildExtractSubReg() argument
5666 buildExtractSubRegOrImm(MachineBasicBlock::iterator MII,MachineRegisterInfo & MRI,const MachineOperand & Op,const TargetRegisterClass * SuperRC,unsigned SubIdx,const TargetRegisterClass * SubRC) const buildExtractSubRegOrImm() argument
5706 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); isLegalRegOperand() local
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| H A D | AMDGPUISelDAGToDAG.cpp | 379 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass() local
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| H A D | AMDGPUInstructionSelector.cpp | 3023 computeIndirectRegIndex(MachineRegisterInfo & MRI,const SIRegisterInfo & TRI,const TargetRegisterClass * SuperRC,Register IdxReg,unsigned EltSize,GISelKnownBits & KnownBits) computeIndirectRegIndex() argument
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| H A D | SIISelLowering.cpp | 4589 computeIndirectRegAndOffset(const SIRegisterInfo & TRI,const TargetRegisterClass * SuperRC,unsigned VecReg,int Offset) computeIndirectRegAndOffset() argument
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| /llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 439 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) getHexagonSubRegIndex() local
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| H A D | HexagonCopyToCombine.cpp | 584 const TargetRegisterClass *SuperRC = nullptr; in combine() local
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| /llvm-project/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 606 const TargetRegisterClass *SuperRC = FindSuitableFreeRegisters() local
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| H A D | RegAllocGreedy.cpp | 1339 getNumAllocatableRegsForConstraints(const MachineInstr * MI,Register Reg,const TargetRegisterClass * SuperRC,const TargetInstrInfo * TII,const TargetRegisterInfo * TRI,const RegisterClassInfo & RCI) getNumAllocatableRegsForConstraints() argument
1441 const TargetRegisterClass *SuperRC = tryInstructionSplit() local
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| H A D | TargetLoweringBase.cpp | 1427 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); findRepresentativeClass() local
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| H A D | MachineVerifier.cpp | 2567 const TargetRegisterClass *SuperRC = visitMachineOperand() local
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| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 437 CodeGenRegisterClass *SuperRC) { in addSuperRegClass() argument
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 684 getSubRegisterClass(const TargetRegisterClass * SuperRC,unsigned SubRegIdx) getSubRegisterClass() argument
[all...] |